Incremental printing of symbolic information – Ink jet – Controller
Reexamination Certificate
2002-10-30
2004-11-09
Nguyen, Lamson (Department: 2853)
Incremental printing of symbolic information
Ink jet
Controller
C310S317000
Reexamination Certificate
active
06814419
ABSTRACT:
BACKGROUND OF THE INVENTION
On Ink Jet Print Heads piezoelectric transducers are used to eject ink drops. Positive and negative voltages in particular waveforms are required for this purpose: the positive voltage to fill the orifices with the ink and the negative voltage to eject the ink drops. The shapes of such waveforms are determined by the type of the ink and the specific characteristics of the print heads. A Head Drive ASIC (HDA) is used to provide such waveforms. The amplitude of the output voltage across each transducer on the print head must be individually adjusted to compensate for sensitivity variations of different piezoelectric elements on the print heads. This can be referred to as “normalization” or “calibration” wherein Head Driver ASIC designs use digital circuitry for the normalization procedure. An alternate method is disclosed which may simplify the circuitry and improve the normalization accuracy.
A simplified block diagram of the circuitry used in prior art Head Driver ASIC and related signal waveforms are shown in
FIGS. 1 and 2
respectively. VPP
10
and VSS
12
are the positive and the negative power supplies with voltages in particular shapes as shown. The piezoelectric transducer has a capacitive load and is shown by a capacitor Cpz
14
. Two switches, switch S
1
16
and switch S
2
18
, connect the transducer to VPP
10
and VSS
12
respectively. The polarity of a signal, called POL (polarity)
20
, determines which power supply (VPP or VSS) is connected to the transducer
14
. The output voltage (Vout)
22
across each transducer
14
should reach a specific level determined by a 6-bit data stored in a 6-bit latch
24
as shown in FIG.
1
. This allows the voltage across each transducer
14
to be trimmed to a determined value in order to compensate for sensitivity variations of different transducers on the print head. This procedure is called “Normalization” or “Calibration”.
Referring once again to
FIGS. 1 and 2
, assuming that the print data is “1”, a signal call SEL (select)
26
goes high at time t
1
28
, switch S
1
16
is closed connecting the output transducer
14
to VPP
10
and the output voltage (Vout)
22
across the transducer
14
follows VPP
10
. VPP
10
has a high slope between t
1
28
and t
2
(fast slew)
30
and after t
2
30
slope is lower for normalization purpose. At time t
2
30
, when the slope of VPP
10
is changed, a signal NOM_CEN (Normalization Counter Enable)
32
goes high and triggers a 6-bit counter
34
. The output of the counter
34
is compared to the normalization data (B
0
B
1
B
2
B
3
B
4
B
5
) stored in the 6-bit latch
24
in the delay circuit
36
(shown in
FIG. 2
) and when it matches that data a signal called NORM_LATCH
38
goes low at time t
3
40
. So basically the delay circuit
36
generates a signal delayed from t
2
30
and the amount of delay is determined by 6-bit data stored in 6-bit latch
24
. At this time (t
3
)
40
the signal NORM_LATCH
38
is used to disconnect the output from VPP
10
and the capacitive load of the transducer
14
keeps the output voltage
22
at this level, so the voltage across the transducer
14
is adjusted by 6-bit normalization data.
At time t
4
42
the POL (polarity) signal
20
goes low and switch S
2
18
is closed connecting the transducer
14
to negative supply VSS
12
and Vout
22
follows VSS
12
. Similarly at time t
5
44
the slope of VSS
12
is changed and the 6-bit counter
34
is triggered again and at time t
6
46
, delayed from t
5
44
based on normalization data B
0
B
1
B
2
B
3
B
4
B
5
, the transducer
14
is disconnected from VSS
12
and keeps its voltage at this level. As a result the output voltage
22
shown in
FIG. 2
is generated across the transducer
14
which is basically shaped by the predetermined shapes of VSS
12
and VPP
10
and its amplitudes are adjusted by “normalization” data.
SUMMARY OF THE INVENTION
Circuitry for providing a method (semi-analog) for normalization procedure of the Head Driver ASIC is disclosed. The circuitry utilizes current DAC's (Digital-to-Analog Converts) to adjust the amplitudes of the voltages across piezoelectric elements, based on predetermined normalization (calibration) data which are stored in separate latches (a different normalization data for each Individual transducer). The transducers all receive their respective calibrated voltage values all at the same time by varying the current slope delivered to each. This method provides more simplicity and more accuracy for normalization procedure and results in better performance then using digital circuitry and digital counters.
REFERENCES:
patent: 5212497 (1993-05-01), Stanley et al.
patent: 6086190 (2000-07-01), Schantz et al.
patent: 6102513 (2000-08-01), Wen
patent: 6104178 (2000-08-01), Sugimoto
patent: 6305773 (2001-10-01), Burr et al.
patent: 6382754 (2002-05-01), Morikoshi et al.
patent: 6412923 (2002-07-01), Kaisha
patent: 2001150666 (2001-06-01), None
Mouttet Blaise
Nguyen Lamson
Xerox Corporation
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