Normalization estimator

Details Normalization estimator Normalization estimator

1991-06-17

1992-09-01

Nguyen, Long T.

Boots, shoes, and leggings

3647462, 364748, G06F 738

Patent

active

051445700

ABSTRACT:
A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.

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patent: 5040138 (1991-08-01), Maher, III

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