Normalization circuitry

Details Normalization circuitry Normalization circuitry

1997-12-05

1999-09-07

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 501

Patent

active

059480491

ABSTRACT:
Normalization circuitry comprises an AND gate for computing the AND of a reference signal generated from an exponent input with a mantissa input, and an OR gate for computing the OR of all the bits of the output of the AND gate. A leading one detector detects the bit position of the leading 1 of the mantissa input, and then generates a signal only one bit at the detected bit position of which is set to 1. A priority encoder then subtracts 1 from the number showing the bit position of the leading 1 counted from the most significant bit (MSB). A one-bit shifter shifts all the bits of the signal except its MSB from the leading one detector one bit position to the right. The normalization circuitry further includes a first selecting circuit for furnishing the output of the one-bit shifter as all the bits of a control signal except its MSB when the output of the OR gate is logic 1, and for furnishing an output of a decoder which decodes the exponent input as all the bits of the control signal except its MSB when the output of the OR gate is logic 0, a shifter for shifting the mantissa input by the shift amount represented by the control signal comprised of the most significant bit of the signal from the leading one detector and all the bits of the output of the first selecting circuit so as to generate a mantissa output, and a second selecting circuit for furnishing a subtraction result obtained by subtracting a binary number from the priority encoder from the exponent input as an exponent output when the output of the OR gate is logic 1, and for furnishing a zero binary number as the exponent output when the output of the OR gate is logic 0.

REFERENCES:
patent: 5187678 (1993-02-01), Hori
patent: 5699285 (1997-12-01), Miyanishi et al.
patent: 5757682 (1998-05-01), Schwarz et al.
patent: 5764549 (1998-06-01), Bjorksten et al.
patent: 5796644 (1998-08-01), Jiang

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