Normalization circuit device of floating point computation devic

Details Normalization circuit device of floating point computation devic Normalization circuit device of floating point computation devic

1996-05-22

1997-12-16

Mai, Tan V.

Boots, shoes, and leggings

364748, G06F 700, G06F 738

Patent

active

056992858

ABSTRACT:
It is an object to realize in a floating point computation device a normalization circuit device which carries out normalization, unnormalization and 0 function operation at high speed. A circuit (3) outputs 1 from the most significant bit for the number obtained by adding 1 to a decimal number value of the exponent part input signal (A). AND operation of the signal (A") and the mantissa part input signal (B) and OR operation of all bits of the value ((3) provide a control signal (G'). A circuit (2) represents in a binary value (B') a number obtained by subtracting 1 from a number value of the bit position of the leading 1 from the most significant bit of the signal (B). A circuit (6) subtracts the valve (B') from the signal (A) and a circuit (7b) selects the signal (H) and a 0 value according to the signal (G') to obtain an exponent part output signal (C) after normalization. A circuit (5) retrieves the respective bit states of the signal B from the most significant bit to render "1" only the bit state of the position of the leading 1. A circuit (7a) selects the signal (B") and a decoded signal (A') according to the signal (G') to obtain a moved amount (D). A shifter (8) shifts the signal (B) according to the signal (D) to obtain a mantissa part output signal (E) after normalization.

REFERENCES:
patent: 4841467 (1989-06-01), Ho et al.
patent: 4994996 (1991-02-01), Fossum et al.
patent: 5103418 (1992-04-01), Birger
patent: 5187678 (1993-02-01), Hori
patent: 5424968 (1995-06-01), Okamoto

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