NOR gate with logical low output clamp

Details NOR gate with logical low output clamp NOR gate with logical low output clamp

1985-06-17

1987-02-03

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307468, 307554, 307555, 307568, H03K 19094, H03K 1920, H03K 508

Patent

active

046410465

ABSTRACT:
A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

REFERENCES:
patent: 4041459 (1977-08-01), Horninger
patent: 4375039 (1983-02-01), Yamauchi
patent: 4445051 (1984-04-01), Elmasry
patent: 4538075 (1985-08-01), Varadarajan

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