Nonvolatile, zero-power memory cell constructed with capacitor-l

Details Nonvolatile, zero-power memory cell constructed with capacitor-l Nonvolatile, zero-power memory cell constructed with capacitor-l

1992-02-14

1992-09-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read only systems

Fusible

365102, 36518911, 3072221, 307451, 307475, G41C 1700

Patent

active

051483912

ABSTRACT:
This disclosure describes a nonvolatile zero-power memory cell circuit constructed from anti-fuses operable at less than full power supply voltage, and which provides full CMOS output voltage levels. The cell comprises a programmable node which is connected to a high voltage line (which during normal operation is at a potential of approximately V.sub.cc /2) via a first antifuse and to a low voltage line (which during normal operation is at ground potential) via a second antifuse. The programmable node is connectable to ground via a field-effect transistor which is controlled by a programming signal. The programmable node may be permanently connected to the high-voltage line by activating the programming signal and raising the voltage on that line to a voltage that is sufficiently high to cause the dielectric of the first antifuse to short. On the other hand, the programmable node may be permanently connected to the low-voltage line by activating the programming signal and raising the voltage on that line to a voltage level that is sufficiently high to cause the dielectric of the second antifuse to short. In order to provide a CMOS compatible outut, the voltage at the programmable node is fed to either a simple voltage translator or to a latched circuit, either of which boosts V.sub.cc /2 outputs to V.sub.cc (the required voltage for CMOS operation).

REFERENCES:
patent: 5065048 (1991-11-01), Asai et al.
patent: 5068553 (1991-11-01), Love
patent: 5099149 (1992-03-01), Smith
patent: 5113097 (1992-05-01), Lee

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