Nonvolatile static random access memory

Details Nonvolatile static random access memory Nonvolatile static random access memory

2000-10-16

2001-09-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

Reexamination Certificate

active

06285586

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory, and more particularly to a Nonvolatile Static Random Access Memory (NVSRAM).
BACKGROUND OF THE INVENTION
There are essentially two types of data memory devices used in computers today, “Nonvolatile” and “Volatile”. Common nonvolatile memory devices include well-known Read Only Memory (ROM) devices that include EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, and Flash EEPROM devices. These nonvolatile memory devices maintain the data stored therein, even when power to the device is removed, thus they are nonvolatile. Volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices. RAM devices in the prior art have been used for temporary data storage, such as during data manipulation, since writing data into, and reading data out of, the device is performed quickly and easily. However, a disadvantage of these devices is that they require the constant application of power, such as in the form of a data refresh signal, to refresh and maintain data stored in the memory cells of the chip. Once power supplied to the device is interrupted, the data stored in the memory cells of the chip is lost.
Flash EEPROMs are most commonly used in all of the nonvolatile memory devices. The Flash EEPROM has an advantage of being nonvolatile, but the flash EEPROM has a problem of endurance. Under repeated cycling program/erase operations, the flash EEPROM is exhausted and results in breaking down, so that the flash EEPROM loses the capability of data storage. In addition, the flash EEPROM relative to DRAM and SRAM needs higher threshold voltage and longer time for programming. Therefore, the speed of the computer will be very slow if the flash EEPROM in used as a memory device.
SRAM having fast data access speed and long lifetime in all of the memory devices is suitable for use in the computer, such as in BIOS. However, the SRAM is a volatile memory device. The data stored in the SRAM will be lost if power is interrupted. Hence, an additional nonvolatile memory device is needed, such as a hard disk, to store data before the power is turned off.
If the SRAM and nonvolatile memory device can be combined, the memory device will have both advantages of the SRAM and the nonvolatile memory device, such as fast data access, long lifetime, and data retention, so that a nonvolatile SRAM will be useful and worthy.
SUMMARY OF THE INVENTION
The present invention provides a nonvolatile static random access memory (NVSRAM) constructed by replacing a transistor in the conventional SRAM cell with a nonvolatile erasable programmable memory transistor (NEPMT), and accompanied by a suitable circuit device. The NVSRAM has the advantages of the SRAM and the nonvolatile memory device, such as fast data access, long lifetime, and nonvolatility.
The present invention provides a nonvolatile static random access memory device adapted for a semiconductor substrate, comprising: A nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain is connected to a first bit line; an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line; a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal; a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.
The present invention also provides a method for operating the above-discussed nonvolatile static random access memory (NVSRAM) device, comprising the steps of:
(1) after the power is turned on, the data stored in the charge storage layer of the nonvolatile erasable programmable memory transistor is read out in a nonvolatile operation mode and is transmitted to a data buffer region, and then the data in the data buffer region is transmitted and stored in the NVSRAM cell in a SRAM operation mode;
(2) after the data is converted, the NVSRAM cell is operated in the SRAM operation mode; and
(3) before power is turned off, the data stored in the NVSRAM cell is read out in the SRAM mode and is transmitted to the data buffer region, and then, the data in the data buffer region is stored in the charge storage layer in a nonvolatile operation mode.


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