Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-02-27
2003-12-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185290, C365S185300, C365S185120, C365S185110
Reexamination Certificate
active
06671208
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor storage device that has a means for executing erase in blocks and a storage contents erase method therefor.
There has recently been a growing demand for a nonvolatile semiconductor storage device capable of executing erase in blocks, intended mainly for portable equipment.
The block erase of a conventional nonvolatile semiconductor storage device capable of executing erase in blocks will be described below with reference to
FIGS. 9A
,
9
B,
10
A,
10
B,
11
,
12
and
13
.
FIG. 9A
shows a typical memory cell structure of an EEPROM (electrically erasable programmable ROM), which is a nonvolatile semiconductor storage device. As shown in this figure, the memory cell has a MOS transistor structure of a two-layer gate constructed of a control gate
701
and a floating gate
702
. This memory cell is covered with an insulating film of SiO
2
or the like. This insulating film serves to provide electrical insulation of each portion that constitutes the memory cell, a function as a capacitor and protection from the external environment. A state in which a comparatively large number of electrons are injected into the floating gate
702
serves as a written state, where the memory cell has a high threshold value. A state in which a comparatively small number of electrons are injected into the floating gate
702
serves as an erased state, where the memory cell has a low threshold value. This difference between the threshold values is utilized for information storage. An operation for determining whether each memory cell is in the written state or in the erased state is a read operation.
Write into the memory cell, i.e., a transition from the erased state to the written state is achieved by injecting electrons into the floating gate.
There have been put into practice several methods for this purpose, and the write by injecting channel hot electrons (CHE) described below is most general. In concrete, by applying a high voltage (10 V, for example) to the control gate
701
, applying a high voltage (6 V, for example) to the drain
705
and setting the source
703
to 0 V, a channel is formed to flow a large current between the drain
705
and the source
703
. That is, electrons move from the source
703
to the drain
705
. The electrons that have moved from the source
703
to the drain
705
become electrons in a high energy state due to the high voltage of the drain
705
. If the energy at this time exceeds the energy barrier of an insulating film
704
, then the electrons can move to the floating gate
702
. With this mechanism, the memory cell is put in the written state by the injection of electrons into the floating gate
702
.
On the other hand, the erase of the memory cell can be achieved by extracting the electrons accumulated in the floating gate
702
. Several methods have been put into practice, and a method for extracting electrons from the source
703
is most general. According to this method, the electrons are moved by the tunnel effect from the floating gate
702
to the source
703
, i.e., the memory cell is erased by, for example, making the control gate
701
have a voltage of 0 V, making the source
703
have a high voltage (12 V, for example) and floating the drain
705
. This is the erase method called the high voltage source erase.
There is also put into practice a negative voltage gate erase, which is a kind of source erase and able to suppress the source voltage low. According to this erase method, the potential of the floating gate
702
is lowered by applying a negative voltage (−10 V, for example) to the control gate
701
, applying a high voltage (5 V, for example) to the source
703
and floating the drain
705
. According to this erase method, a similar tunnel effect can be obtained by a source voltage lower than that of the method of making the control gate
701
have a voltage of 0 V, and the memory cell erase can be achieved. This negative voltage gate erase is also an erase method that applies a high voltage to the source. In order to distinguish this method from the source erase that is not the negative voltage gate erase, there will be provided the description that the former is referred to as a negative voltage gate erase and the latter is referred to as a high voltage source erase in distinction.
Next,
FIG. 9B
shows the array structure of a flash memory. This figure shows the array structure of a NOR type flash memory, which is a typical flash memory. Row select lines
711
,
712
,
713
,
714
,
715
,
716
, . . . are connected to the control gates of a plurality of memory cells, and column select lines
732
,
731
, . . . are connected to the drains of the plurality of memory cells. The plurality of row select lines
711
, . . . ,
716
, . . . and the plurality of column select lines
732
,
731
, . . . constitute a matrix, forming a memory array. In the flash memory, the memory cells in an identical block share a source line
741
, and this facilitates easy batch erase of the cells in a block and also enables a substantial reduction in the memory array area.
During write in this flash memory cell array, the write is effected only on the cell of which both the row select line and the column select line are selected, and therefore, write in bits can be achieved. In the case of division into blocks that respectively have a common source line as in a flash memory, erase is executed by block erase for erasing in a batch all the memory cells in a block. It is to be noted that the block erase can be achieved with a lower source voltage than in the case of the high voltage source erase when the negative voltage gate erase is used, and therefore, only the memory cell to the gate of which a negative voltage is applied can be erased. It is also possible to execute sector erase for selectively erasing only a specified sector by dividing the block that shares a source line into sectors that are more minute erase units.
During the source erase of an EEPROM, a tunnel current between bands (BTBT: Band-To-Band Tunneling current, referred to as a BTBT current hereinafter) described in detail later cannot be avoided in the overlap region of the floating gate and the source diffusion layer. Accordingly, there is a reduction in the current efficiency of the erase operation, i.e., the ratio of electric charges to be extracted from the floating gate with respect to the charges consumed by the high voltage applied to the source.
This BTBT current will be described with reference to
FIGS. 10A and 10B
.
FIG. 10A
schematically shows the state in the vicinity of the source
703
in the aforementioned erase operation. This erase operation is achieved by extracting electrons from the floating gate
702
to the source
703
by the FN (Fowler-Nordheim) tunneling phenomenon. An electron A inside the floating gate
702
is moved to the source
703
by the voltage applied during erase according to the FN tunneling phenomenon. This movement of the electron A is the erase operation.
However, by applying a high voltage to the source
703
, a potential slope, i.e., band bending is caused by an electric field that concentrates on the surface and its vicinities of the overlap portion of the floating gate
702
and the source
703
. This increases the electron potential in a valence band, and if the potential becomes higher than the conduction band of the N
+
region, then there appears an electron (electron B in
FIGS. 10A and 10B
) that passes through the bandgap between the valence band and the conduction band by the band-to-band tunnel effect and moves to the conduction band. This is the BTBT current, occurring concurrently with a hole.
FIG. 10B
shows an energy band diagram of the state of electron energy at this time. The electron A is an electron that moves from the floating gate
702
to the source
703
during erase. The electron B moves in the direction of arrow as a consequence of an increase in the electron potential in the valence band due to band bending &psgr;s. Th
Satoh Takayuki
Sumitani Ken
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Tran Andrew Q.
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