Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-05-25
2001-04-10
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S200000
Reexamination Certificate
active
06215699
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor storage device having a redundancy function, and in particular, to a nonvolatile semiconductor storage device capable of executing erase and write operations in blocks.
A flash EEPROM (collectively erasing type electrically erasable programmable read-only memory) has conventionally been mainly used as a code storage for a portable telephone or BIOS (basic input output systems). However, in recent years, there has been a growing demand for the use of the flash EEPROM as a data storage for a digital still camera or the like. The flash EEPROM for data storage use is required to execute rewriting particularly in blocks of a small size.
As a flash EEPROM that satisfies the above requirement, there is an AND type flash memory announced as a communication technique at the meeting of The Institute of Electronics, Information and Communication Engineers in May 1995. The AND type flash memory is a flash EEPROM that has a parallel line structure in which the data line and the source line are laminated and executes writing and erasing by the FN (Fowler-Nordheim) tunnel effect.
FIG. 4
shows the array structure of one block of the AND type flash memory. In
FIG. 4
, n+1 (=64) memory cells MC
00
, MC
01
, . . . , MC
0
n
are connected parallel between a sub-data line SD
0
that diverges from a main data line D
0
via a drain side selection transistor DT
0
and a sub-source line SS
0
that diverges from a main source line S via a source side selection transistor ST
0
. Then, by using this as one unit (AND unit), m+1 (corresponding to 512 bytes) AND units are arranged on n+1 (=64) word lines WL
0
, WL
1
, . . . , WLn. Then, a plurality of blocks, which are each constructed of (n+1)×(m+1) memory cells MC served as one block, are arranged with main data lines D
0
through Dm commonly owned, constituting the AND type flash memory array.
As described above, the data lines are stratified into main data lines D
0
, D
1
, . . . , Dm and sub-data lines SD
0
, SD
1
, . . . , SDm, while the source lines are stratified into the main source line S and the sub-source lines SS
0
, SS
1
, . . . , SSm. By disconnecting the sub-data line SD of the non-selected block from the main data line D by the drain side selection transistor DT and disconnecting the sub-source line SS from the main source line S by the source side selection transistor ST, only the selected block can be connected to the main data line D and the main source line S. As a result, even if the write and erase operations are executed every one word line WL, the memory cells MC connected to the word line WL of the non-selected block receives no influence of disturbance. This allows the achievement of the write and erase operations in batches of sectors SC constructed of the memory cells MC (for example, memory cells MC
00
, MC
10
, . . . , MCm
0
) comprised of a transistor whose gate is connected to one word line WL (for example, word line WL
0
).
FIGS. 5A and 5B
show the fundamental operation of the AND type flash memory. The AND type flash memory executes the writing and erasing by the FN tunnel effect as described earlier. As shown in
FIG. 5A
, the writing is executed by reducing the threshold voltage through applying a high voltage Vd to the drain
1
of the transistor that constitutes the memory cell MC so as to discharge electrons from the a floating gate
2
to the drain
1
side. In contrast to this, as shown in
FIG. 5B
, the erasing is executed by increasing the threshold voltage through applying a high voltage Vg to a gate
3
so as to inject electrons from a substrate
4
into the floating gate
2
. In order to achieve the write and erase operations in batches of sectors while preventing the disturbance, no voltage is applied to the substrate
4
in either operation.
In the AND type flash memory, which can execute write and erase operations in batches of sectors SC as described earlier, the redundancy processing is executed in batches of sectors SC.
FIG. 6
shows the principle of the redundancy processing of the AND type flash memory. During the write and erase operations, if the sector relevant to the selected word line WL is a defective sector
6
a
, then this defective sector
6
a
is replaced by a redundancy sector
7
provided inside a memory array
5
.
By this operation, the redundancy replacement block can be reduced to one sector
6
at a minimum, so that the yield can be improved by virtue of the size of one or more replacement sectors smaller than in the case of replacement in redundancy use blocks constructed of a plurality of redundancy sectors.
As a flash EEPROM that is able to execute the write and erase operations in small-scale units and to achieve a higher integration than in the AND type flash memory, there is a virtual ground type flash memory. As described in detail later, this virtual ground type flash memory is a high-density memory array that has a reduced number of contacts (bit line contacts) of bit line with metal electrodes and needs no source line. This high-density arrangement is achieved by forming the bit line with diffused layer wiring for the stratification of the bit line and using an adjacent bit line as a source line.
It is to be noted that this memory array receives a great influence of disturbance in selecting the bit line during the write and erase operations, and accordingly, there is needed a method for avoiding the influence of the disturbance. As an example of the method, there is an ACT type flash memory employing an ACT (Asymmetrical Contactless Transistor) published in “A New Cell Structure for Sub-quarter Micron High Density Flash Memory” IEDM Technical Digest, pp. 269-270, 1995.
The ACT type flash memory uses the FN tunnel effect for the write and erase operations and has a virtual ground array structure in which an identical bit line is commonly owned by adjacent two memory cells connected to an identical word line WL as its memory array structure as shown in FIG.
7
. As described above, the number of bit line contacts is reduced by commonly using the sub-bit line for two memory cells and using the diffusion layer for the sub-bit line, enabling high integration through the substantial reduction in the memory cell area. It is to be noted that
FIG. 7
shows a main bit line MBLx (x: integer), a sub-bit line SBLx formed of a diffusion layer, a word line WLx and a select gate selection line SGx. The mark<represents the contact of the main bit line MBLx with the sub-bit line SBLX in different strata.
The ACT type flash memory having the above construction operates as follows. It is to be noted that the FN tunnel effect is used for the write and erase operations. During the write operation, as shown in
FIG. 8A
, a negative voltage (−9 V in the figure) is applied to the gate (word line WL) of the transistor that constitutes each memory cell, a positive voltage (+5 V in the figure) is applied to the sub-bit line SB on the drain side and the sub-bit line SB on the source side is put in the floating state. Then, the FN tunnel effect occurs between the n
+
side of the sub-bit line SB located on the drain side and the floating gate FG, thereby extracting electrons from the floating gate FG to the sub-bit line SB located on the drain side. Thus, the writing is executed by reducing the threshold voltage of the transistor.
During the erase operation, as shown in
FIG. 8B
, a high positive voltage (10 V in the figure) is applied to the gate (word line WL) of the transistor that constitutes each memory cell, a negative voltage (−8 V in the figure) is applied to the sub-bit lines SB on the drain and source sides and to the substrate (P
−
region) Then, the FN tunnel effect occurs between the channel region of the substrate and the floating gate FG, thereby injecting electrons into the floating gate FG. Thus, the erasing is executed by increasing the threshold voltage of the transistor. No description is provided for the read and verif
Mai Son
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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