Static information storage and retrieval – Floating gate – Particular connection
Patent
1998-06-04
2000-03-07
Nelms, David
Static information storage and retrieval
Floating gate
Particular connection
36518503, 257288, 257316, G11C 1604
Patent
active
060348941
ABSTRACT:
In a NAND cell type of EEPROM memory which has an STI (Shallow Trench Isolation) structure and uses memory cells into which two- or more-value data can be rewritten through the use of floating channel writing techniques, a plurality of floating gate electrodes are formed above the surface of an Si substrate with a tunnel oxide interposed therebetween. Trenches are formed in portions of the surface of the Si substrate each of which is located between floating gate electrodes arranged in one direction. In each trench, a conductive material is buried to form a buried electrode which is externally impressed with a low voltage. This boots the channel potential of nonselected cells, preventing erroneous writing without increasing the cost per bit.
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J.D. Choi, et al., "A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance," Symposium on VSLI Technology Digest of Technical Papers. pp. 238-239.
Maruyama Tohru
Shirota Riichiro
Ho Hoai V.
Kabushiki Kaisha Toshiba
Nelms David
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