Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-02-14
2001-04-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C257S288000, C257S316000
Reexamination Certificate
active
06222769
ABSTRACT:
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 10-113413, filed Apr. 23, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor storage device. More particularly, the present invention relates to a NAND cell type of EEPROM (Electrically Erasable Programmable Read Only Memory) which has an STI (Shallow Trench Isolation) structure and uses memory cells which permit two or more valued data to be electrically rewritten into through the use of techniques of writing into the floating channel.
Conventionally, as a nonvolatile semiconductor storage device which is electrically rewritable and allows a high packing density, a NAND cell type of EEPROM is known in which a plurality of memory cells are connected in series. In this semiconductor storage device, each of the memory cells has a stacked gate structure in which a floating gate and a control gate are stacked with an insulating film interposed therebetween. In addition, the memory cells are connected in series in such a way that adjacent cells share a source/drain diffused region. The memory cells that are connected in series forms a unit. The memory cells as a unit are connected to a bit line (data line), forming a NAND type cell (hereinafter referred to as a NAND cell). The NAND cells are arranged in a matrix to form a memory cell array.
That is, each of NAND cells arranged in each column in the memory cell array has a drain diffused region at its one end connected to a bit line through a select gate and a source diffused region at its other end connected to a common source line (reference potential supply line) through a select gate. The control gates of memory cells arranged in a row are connected in common to a control gate line (word line) and the control electrodes of select gates arranged in the row direction are connected in common to and a select gate line.
If, in the NAND cell type of EEPROM, lower voltage operation were realized, a column decoder connected to the bit lines could be formed from Vcc-operated transistors. This would help reduce the area of peripheral circuitry and the chip size.
From this point of view, in recent years, a floating channel writing method has been proposed and put to practical use. The floating channel writing method is described as follows.
FIG. 1
shows an equivalent circuit of the memory cell section of a NAND cell type of EEPROM. In this figure, BL (BL
1
, BL
2
, BL
3
, . . . ) denotes a bit line, SG (SG
1
, SG
2
) denotes a select gate, CG (CG
1
to CGn) denotes a word line, and SL denotes a source line.
In normal data write operations, the cells are written into in the order of arrangement beginning with the cell that is the farthest from the corresponding bit line BL. In random writing, on the other hand, the cells between the bit line BL and the source line SL are written into in a random order. First, 0 volts are applied to the select gates on the source line SL side to turn their associated transistors off. In this state, 0 volts are applied to a bit line BL associated with a NAND cell containing a memory cell into which a 0 is to be written. To a bit line associated with a NAND cell containing a memory cell into which a 1 is to be written is applied a voltage which is larger than or equal to the select gate voltage on the drain diffused region side. In this manner, a selection between writing and nonwriting is made for each bit line. Alternatively, by applying to the bit line a potential which, even if it is lower than the select gate voltage on the drain diffused region side, permits the select gate SG to turn off, a selection between writing and nonwriting is made for each bit line.
That is, in this state, a potential that permits memory cells to turn on is applied to all the word lines CG in a selected block (when a write voltage Vpp or a nonselected word-line voltage Vpass is applied, memory cells are brought to the on state at a certain potential when the voltage pulse is increasing to a maximum). Then, 0 volts are transferred to the channel of a NAND cell connected to a bit line for writing a 0. On the other hand, to the channel of a NAND cell connected to a bit line for writing a 1 a certain initial potential (the potential on that bit line minus the threshold of the select gate) is transferred from that bit line through the select gate SG on the bit line side. Thus, the NAND cell connected to the bit line for writing a 1 become floating. At this point, 0 volts or a certain positive potential is applied to the source line SL to turn off the select gate on the source diffused region side.
Next, the write voltage Vpp is applied to a selected word line associated with the memory cell into which a 0 is to be written. As a consequence, a 0 will be written into the selected memory cell that is connected to the selected bit line supplied with 0 volts. At this point, it is required that the channel potential of nonselected memory cells which are associated with the selected word line but are not to be written with a 0 (memory cells in which their associated select gates SG on the bit line side are turned off and hence their channels are in the floating state) be sufficiently large so that a 0 will not be written into (so that variations in threshold will fall within an allowable range). In the case of these memory cells, as the difference between the write voltage Vpp and the channel potential Vch becomes smaller, variations in threshold become smaller. For this reason, a certain voltage Vpass is applied to nonselected word lines which are not associated with a memory cell into which a 0 is to be written. By so doing, the channel potential of the memory cells is increased from an initial potential to a certain potential by capacitive coupling of their floating channels with the nonselected and selected word lines. In this case, the greater the voltage Vpass, the smaller the variations in threshold become.
Of memory cells connected with the selected bit line supplied with 0 volts, memory cells into which a 0 is not to be written are also supplied with the voltage Vpass. In this case, the greater the voltage Vpass, the easier the variations in threshold become to occur.
Thus, the minimum and maximum values of the voltage Vpass are determined taking these conditions into consideration. In order to reduce the variations in the threshold of memory cells into which a 0 is to be written and errors associated with writing, a step-up method is normally employed in which the voltages Vpass and Vpp are each optimized for their initial voltage, step voltage, final voltage, and pulse width.
Data erase includes batch erase by which all the memory cells of a NAND cell are simultaneously erased and block erase in byte units. In the case of batch erase, all the control gates (or all the control gates in a selected block) are set to 0 volts and all the selected gates SG are supplied with the voltage Vpp or placed in the floating state. The bit lines and the source line SL are made floating and P-well regions are impressed with a high voltage of, for example, 20 volts. Thereby, in all the memory cells (or all the memory cells in a selected block), electrons are forced from the floating gate into the P-well region, shifting the threshold in the negative direction. In the case of block erase, it is required that the control gates in a nonselected block be impressed with a high voltage of, for example, 20 volts or maintained floating.
For data reading, a read voltage (for example, 4.5 volts) is applied to the select gates SG
1
and SG
2
and the word lines CG associated with nonselected memory cells other than a selected memory cell, thereby turning the nonselected memory cells on. On the other hand, 0 volts are applied to the word line associated with the selected memory cell. By sensing a current flowing through the bit line, discrimination between a 0 and a 1 can be made.
Such a NAND cell type EEPROM writing method (floating cha
Maruyama Tohru
Shirota Riichiro
Ho Hoai V.
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Nelms David
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