Nonvolatile semiconductor storage device having a low...

Details Nonvolatile semiconductor storage device having a low... Nonvolatile semiconductor storage device having a low...

2008-01-03

2010-02-02

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S225700, C365S051000, C365S205000, C365S208000, C365S207000, C365S190000

Reexamination Certificate

active

07656738

ABSTRACT:
A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data from the memory cell. In addition, a write bit-line is arranged in a direction perpendicular to the word-line to write data to the memory cell. The read bit-line pair includes a true and a complementary read bit-line. One of the true and complementary read bit-lines is connected to the memory cell connected to an even-numbered word-line. The other one is connected to the memory cell connected to an odd-numbered word-line.

REFERENCES:
patent: 2006/0133127 (2006-06-01), Nakano et al.
patent: 2008/0165564 (2008-07-01), Namekawa
U.S. Appl. No. 11/833,054, filed Aug. 2, 2007, Toshimasa Namekawa, et al.
U.S. Appl. No. 11/738,774, filed Apr. 23, 2007, Hiroaki Nakano, et al.
Hiroshi Ito, et al., “Pure CMOS One-time Programmable Memory using Gate-Ox Anti-fuse”, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004, pp. 469-472.
U.S. Appl. No. 11/971,425, filed Jan. 9, 2008, Matsufuji, et al.
U.S. Appl. No. 12/040,297, filed Feb. 29, 2008, Namekawa.
U.S. Appl. No. 12/140,071, filed Jun. 16, 2008, Matsufuji et al.

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