Nonvolatile semiconductor storage device capable of...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185220, C365S189050

Reexamination Certificate

active

07855915

ABSTRACT:
A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

REFERENCES:
patent: 6738281 (2004-05-01), Yokozeki
patent: 7505315 (2009-03-01), Honma et al.
patent: 7554849 (2009-06-01), Honma et al.
patent: 7589997 (2009-09-01), Honma et al.
patent: 2004-192789 (2004-07-01), None
patent: 2009-64530 (2009-03-01), None

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