Nonvolatile semiconductor storage device capable of...

Details Nonvolatile semiconductor storage device capable of... Nonvolatile semiconductor storage device capable of...

2001-09-19

2002-11-26

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S203000

Reexamination Certificate

active

06487124

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor storage device of a virtual ground system and a read method for the nonvolatile semiconductor storage device.
There has conventionally been known a semiconductor storage device intended for preventing the flow of a current from a word line to a bit line and a virtual GND line (Japanese Patent Laid-Open Publication No. HEI 6-68683). In this semiconductor storage device, as shown in
FIG. 7
, memory cell transistors are connected in an array form to bit lines
1
through
4
and virtual GND lines
5
through
9
. Moreover, metal bit lines
10
through
12
are provided commonly for two bit lines of each block constructed of two bit lines (bit lines
2
and
3
, for example). A precharge circuit
17
, which has transistors
14
through
16
connected to the metal bit lines
10
through
12
, respectively, is arranged between a Y gate
13
and the memory cell array.
Metal virtual GND lines
18
and
19
are provided one per block constructed of adjoining two virtual GND lines (virtual GND lines
6
and
7
, for example). The metal virtual GND lines
18
and
19
are connected to precharge select circuits
20
and
21
, respectively. It is to be noted that reference numerals
22
and
23
denote bit line select lines, numerals
24
and
25
denote virtual GND line select lines, and a numeral
26
denotes a word line.
When, for example, a memory cell transistor
27
is read in the semiconductor storage device that has the aforementioned construction, the voltages of the word line
26
, the virtual GND line select line
24
and the bit line select line
22
are pulled up to a Vcc level. The voltages of the virtual GND line select line
25
and the bit line select line
23
are pulled down to the GND level. In the above case, only the voltage of the metal virtual GND line
18
is pulled down to the GND level by the precharge select circuit
20
, while the voltages of all the other virtual GND lines
19
are set to a precharge level by the precharge select circuit
21
. By this operation, only the voltages of the two virtual GND lines
6
and
7
that constitute one block come to have the GND level, while the voltages of other virtual GND lines
5
,
8
and
9
come to have the precharge level. Moreover, the metal bit line
11
is selected by a Y gate
13
. In the above case, the voltage of the bit line select line
22
has the Vcc level, and the bit line select line
23
has the GND level, as described above. Consequently, a transistor
28
is turned OFF, and a transistor
29
is turned ON. Therefore, the bit line
3
is connected to the metal bit line
11
via the transistor
29
so as to be put in a selected state. By this operation, the memory cell transistor
27
is brought into the selected state.
There is another semiconductor storage device as shown in
FIG. 8
, in which the current from the word line is prevented from flowing into the bit line and the virtual GND line (Japanese Patent Laid-Open Publication No. HEI 10-11991). As shown in
FIG. 8
, this semiconductor storage device is constituted roughly of a NOR type cell array constructed of memory cell transistors M
01
through Mn
8
, a select circuit
31
, a precharge circuit
32
, a sense amplifier
33
, a select circuit
34
, a precharge circuit
35
and so on. There are further provided bit lines and virtual GND lines D
1
through D
9
, word lines WD
0
through WDn, bit-line select transistors S
1
through S
6
, virtual GND line select transistors S
11
through S
17
, bit line select lines BS
0
and BS
1
and virtual GND line select lines BS
2
and BS
3
.
Furthermore, bit line select circuits SEL
1
and SEL
2
, which are respectively constructed of three bit line select transistors S
1
through S
3
and S
4
through S
6
, are connected to memory cell transistors M arranged in four columns and select the bit lines and virtual GND lines D in units of columns. Among the bit line select transistors S
1
, S
2
and S
3
that constitute the bit line select circuit SEL
1
, the bit line select transistors S
1
and S
3
have their gates commonly connected to a bit line select line BS
0
, have their sources connected to a select circuit
31
via a bit line Y
1
and have their drains connected to the bit lines and virtual GND lines D
2
and D
4
. The bit line select transistor S
2
has its gate connected to a bit line select line BS
1
, has its source connected to a select circuit
31
via a bit line Y
1
and has its drain connected to the bit line and virtual GND line D
3
.
When, for example, the memory cell transistor M
01
is read in the semiconductor storage device having the aforementioned construction, the voltages of the word line WD
0
connected to the gate of the memory cell transistor M
01
, the bit line select line BS
0
connected to the gate of the bit line select transistor S
1
whose drain is connected to the drain (or source) of the memory cell transistor M
01
and the virtual GND line select line BS
3
connected to the gate of the virtual GND line select transistor S
11
whose drain is connected to the source (or drain) of the memory cell transistor M
01
are pulled up to the VCC level, turning ON the bit line select transistor S
1
and the virtual GND line select transistor S
11
.
At the same time, the voltages of the bit line select line BS
1
and the virtual GND line select line BS
2
are pulled down to the GND level, turning OFF the bit line select transistors S
2
and S
5
and the virtual GND line select transistors S
12
, S
13
, S
15
and S
16
. The select circuit
31
connects the bit line Y
1
to the sense amplifier
33
and connects the bit line Y
2
to the precharge circuit
32
. Furthermore, the select circuit
34
connects a virtual GND line VG
1
to the virtual GND and connects the virtual GND lines VG
2
and VG
3
to the precharge circuit
35
.
Therefore, the bit line Y
1
and the bit line and virtual GND line D
2
are connected together by the bit line select transistor S
1
turned ON. The virtual GND line VG
1
and the bit line and virtual GND line D
1
are connected together by the virtual GND line select transistor S
11
turned ON. As a result, among the bit line and virtual GND lines D
1
and D
2
, the line “D
2
” becomes the bit line, and the line “D
1
” becomes the virtual GND line, bringing the memory cell transistor M
01
into the selected state.
However, the conventional semiconductor storage device of the virtual GND system has the problem that misread will possibly occur due to a leak current from the memory cell transistors
30
and M
04
, which share the word lines WL and WD
0
with the memory cell transistors
27
and M
01
.
First of all, in the case of the aforementioned semiconductor storage device of Japanese Patent Laid-Open Publication No. HEI 6-68683, when the memory cell transistor
27
is selected in
FIG. 7
, the voltage of the virtual GND line
8
is also pulled up to the precharge level Vpc since the virtual GND line select line
24
has the voltage level of Vcc. Therefore, when the memory cell transistor
30
is ON, a superfluous current flows into the metal bit line
11
through the memory cell transistor
30
, as a consequence of which the reduction in the potential of the metal bit line
11
is hindered when the memory cell transistor
27
is ON, possibly causing an operation as if the memory cell transistor
27
were an OFF cell.
Next, in the case of the aforementioned semiconductor storage device of Japanese Patent Laid-Open Publication No. HEI 10-11991, when the memory cell transistor M
01
is selected in
FIG. 8
, the bit line select transistor S
3
is also turned ON concurrently with the turning-on of the bit line select transistor S
1
. In this case, when the memory cell transistor M
04
connected to the selected word line WD
0
is ON, a current flows into the bit line Y
1
via the memory cell transistor M
04
and the bit line select transistor S
3
since the non-selected bit line D
5
has the precharge level, as a consequence of which the reduction in the potential of the bit lin

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