Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-06-07
2003-01-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S185260
Reexamination Certificate
active
06512692
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a floating gate type nonvolatile semiconductor storage device and a write test method for the device.
Conventionally, as a virtual ground type flash memory intended for a high integration density, there can be enumerated the ACT (Asymmetrical Contactless Transistor) type flash memory published in, for example, IEDM Technical Digest, pp. 269-270, 1995 “A New cell Structure for Subquarter Micron High Density Flash Memory” and the Transactions of the Institute of Electronics, Information, and Communication Engineers, ICD 97-21, P37, 1997 “Examination of ACT Type Flash Memory Sense System”.
This ACT type flash memory utilizes the FN (Fowler-Nordheim) tunneling phenomenon for the write (programming)/erase (erasing) operation and is expected to be used as a data storage type.
FIG. 8
is a block diagram of the ACT type flash memory. The ACT type flash memory will be described below with reference to FIG.
8
.
In
FIG. 8
where the ACT type flash memory cells are arranged in an array form, there are shown a main bit line MBL formed of a metal layer, a sub-bit line SBL formed of a diffusion layer, a word line WL and a select gate signal line SG. The sign ▪ indicates a metal-to-diffusion-layer contact, while the sign &Circlesolid; indicates a diffusion layer connection.
As described above, the ACT type flash memory having the above-mentioned construction utilizes the FN tunneling phenomenon for the write and erase operations, and the array construction is provided in the form of a virtual ground array mechanism where an identical bit line is shared by two memory cells. As described above, in the ACT type flash memory, the number of contacts is reduced by sharing the two bit lines MBL and SBL by the memory cells and forming part of the bit line of a diffusion layer, enabling the achievement of high density integration with a considerably reduced array area.
FIGS. 9 through 11
show the voltage application state during the read operation/write operation/erase operation in the ACT type flash memory. The read operation/write operation/erase operation of the ACT type flash memory will be described in detail below with reference to
FIGS. 9 through 11
.
As shown in
FIG. 9
, in the read operation, a voltage of 0 V is applied to adjoining three main bit lines MBL
0
, MBL
1
and MBL
2
. Two main bit lines MBL
3
and MBL
4
, which are further adjacent to the main bit line MBL
2
, are precharged with 1 V and thereafter put into a floating state. A voltage of 1 V is applied to one main bit line MBL
5
that is further adjacent to the main bit line MBL
4
. Two main bit lines MBL
6
and MBL
7
, which are further adjacent to the main bit line MBL
5
, are precharged with 1 V and thereafter put into the floating state. Then, the voltage application pattern of the eight main bit lines MBL of the main bit lines MBL
0
through MBL
7
will be repeated subsequent to the main bit line MBL
8
.
In the above case, a potential difference of 1 V is generated between the source and the drain of ACT type flash memory cells
1
and
1
enclosed by the sign ◯ in FIG.
9
. Therefore, if the threshold voltage of the ACT type flash memory cells
1
and
1
is lower than the voltage (3 V) of the word line WL
0
, then a cell current flows, as a consequence of which the drain voltage is lowered. If the threshold voltage of the ACT type flash memory cells
1
and
1
is higher than the voltage (3 V) of the word line WL
0
, then no cell current flows, as a consequence of which the drain voltage is not lowered. Accordingly, by sensing the difference in the drain voltage by means of a sense amplifier (not shown) via the main bit lines MBL
3
and MBL
7
with a voltage of 3 V applied to the select gate signal line SG, the information written in the ACT type flash memory cells
1
and
1
is read.
In the write operation, as shown in
FIG. 10
, a high voltage of 5 V is applied to the n
+
side of the sub bit lines (diffusion bit lines) SBL
2
and SBL
5
of the ACT type flash memory cells
2
and
2
to undergo the write operation in a state in which a negative voltage of −8 V is applied to the word line WL
0
. In the above case, electrons are to be extracted from the floating gates of the ACT type flash memory cells
2
and
2
toward the sub bit lines SBL
2
and SBL
5
by the FN tunneling phenomenon, as a consequence of which the threshold voltage of the ACT type flash memory cells
2
and
2
is lowered. In general, the threshold voltage of the ACT type flash memory cells
2
and
2
is controlled to about 1 V to 2 V by the write operation.
In the erase operation, as shown in
FIG. 11
, a voltage of −8 V is applied to the sub-bit line SBL in a state in which a high voltage of 10 V is applied to the word lines WL
0
through WL
31
inside one block to undergo the erase operation demarcated by the select gate signal line SG, and a voltage of −8 V is applied to the substrate of the ACT type flash memory cell. In this case, electrons are to be injected from the substrate (channel region) of each ACT type flash memory cell inside one block to undergo the erase operation toward the floating gate by the FN tunneling phenomenon, as a consequence of which the threshold voltage of each ACT type flash memory cell is raised. In general, the threshold voltage of each ACT type flash memory cell is controlled to about 4 V to 6 V by the erase operation.
In the case of
FIG. 11
, a voltage of 0 V is applied to the select gate signal lines SG
0
and SG
0
, and a voltage of −8 V is applied to the select gate signal lines SG
1
and SG
1
, consequently turning on select transistors
3
and
4
whose gates are connected to the select gate signal lines SG
0
and SG
0
. Therefore, a block
0
is selected, and all the ACT type flash memory cells inside the block
0
are erased in a batch. In the above case, the sources and the drains of all the ACT type flash memory cells in the non-selected state, which are put into a high impedance state, are not erased.
As the row decoder circuit of the present ACT type flash memory, there is the following one as shown in FIG.
12
. This row decoder circuit
11
is constructed roughly of a driver section
12
for outputting various voltages to the word line WL, a control voltage circuit section
13
, a selecting voltage circuit section
14
, a non-selecting voltage circuit section
15
, a predecoder section
16
and a block decoder section
17
.
FIG. 13
shows a circuit diagram of a control voltage circuit
0
that constitutes the control voltage circuit section
13
. This control voltage circuit is a circuit for outputting a control signal for turning on and off a P-channel MOS (Metal Oxide Semiconductor) transistor and an N-channel MOS transistor that constitute the driver section
12
of the row decoder
11
. Then, output signals hrda
0
and hrdab
0
are generated by inputting an input signal pre
0
(an output signal of a predecoder
0
). The input signals other than the input signal pre
0
and the power source are common to each control voltage circuit.
FIG. 14
shows a circuit diagram of a selecting voltage circuit
0
that constitutes the selecting voltage circuit section
14
. This selected voltage circuit outputs an application voltage to be applied to the selected word line WL via the driver section
12
. Then, an output signal hhvx
0
is generated by inputting an input signal se
10
(an output signal of a block decoder
0
). The input signals other than the input signal se
10
and the power source are common to each selecting voltage circuit.
FIG. 15
shows a circuit diagram of the non-selecting voltage circuit
0
that constitutes the non-selecting voltage circuit section
15
. This non-selected voltage circuit outputs an application voltage to be applied to the non-selected word line WL via the driver section
12
. Then, an output signal hnn
0
is generated by inputting an input signal se
10
(the output signal of the block decoder
0
). The input signals other than the input signal se
10
and the power so
Ito Nobuhiko
Yamauchi Yoshimitsu
Le Thong
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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