Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-06-25
2004-05-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185250
Reexamination Certificate
active
06738292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, such as a flash memory device. More specifically, the present invention relates to a nonvolatile semiconductor storage device capable of reducing a stress of a peak inverse voltage which may be caused due to a high voltage applied inside of a high-voltage generation circuit.
2. Description of the Related Art
In general, a flash memory device has electrical writing and erasing functions. Many flash memories incorporate a high-voltage generation circuit (hereinafter, referred to as a pump circuit) for generating a high voltage, which is necessary for writing and erasing operations.
Hereinafter, such a conventional flash memory is described with reference to FIG.
3
. The conventional flash memory device shown in
FIG. 3
includes a plurality of memory blocks B
1
, B
2
, . . . , which have identical structures. Each of the memory blocks B
1
, B
2
, . . . , includes a memory array M
1
. The memory array M
1
includes a plurality of word lines WL and a plurality of bit lines BL, which are arranged so as to cross each other (in this example, at right angles) such that each memory cell S can be selected. Each word line WL is connected to a gate of a memory cell S, and each bit line BL is connected to a drain of a memory cell S. Further, the word lines WL are connected to a row decoder XD which selects any of the word lines WL according to a row address input from an external circuit. The bit lines BL are connected to a column decoder YD which selects any of the bit lines BL according to a column address input from an external circuit. Pump circuits PV
1
and PV
2
are connected to the respective memory blocks B
1
, B
2
, . . . , for supplying a voltage necessary for writing or erasing data in a memory array. A voltage generated by the first pump circuit PV
1
is supplied to the row decoder XD of each memory block, and a voltage generated by the second pump circuit PV
2
is supplied to the column decoder YD of each memory block. In the example described below, the flash memory device includes a plurality of memory blocks B
1
and B
2
. However, the number of memory blocks included in the flash memory device is not limited to two, but may be three or more.
In the above flash memory device, in order to write data in a memory array of each memory block, for example, a voltage of 12 V is generated by the first pump circuit PV
1
, and the generated voltage is supplied to a certain word line WL through a row decoder XD of a selected block. Concurrently, for example, a voltage of 6 V is generated by the second pump circuit PV
2
, and the generated voltage is supplied to a certain bit line BL through a column decoder YD of the selected block. As a result, data is written in a memory cell S located at the intersection of the above word line WL and bit line BL.
Hereinafter, the structures of the first pump circuit PV
1
and the second pump circuit PV
2
are described with reference to FIGS.
4
(
a
) and
4
(
b
). Herein, the first pump circuit PV
1
and the second pump circuit PV
2
have the same structure. Each of the first pump circuit PV
1
and the second pump circuit PV
2
has multiple stages (n stages) of basic pump cells. As shown in FIG.
4
(
a
), each pump cell includes a pair of capacitors (c
1
and c
2
; c
3
and c
4
; . . . , cm and cn) and a pair of transistors (s
1
and t
1
; s
2
and t
2
; . . . , sn and tn).
In the basic pump cell of the first stage, a capacitor c
1
is a capacitor for increasing the voltage. A capacitor c
2
, which is also a capacitor for increasing the voltage, receives a clock signal CLK
2
at one of its electrodes. The other electrode of the capacitor c
2
is connected to a node chg
1
which connects the basic pump cell of the first stage to a basic pump cell of a subsequent stage, and is connected to a gate of a transistor s
1
. With such a structure, the basic pump cell of the first stage increases the potential at the node chg
1
. A transistor t
1
of the first basic pump cell is an equalizing transistor. The source of the equalizing transistor t
1
is connected to a node N
1
which connects the first basic pump cell to the power supply voltage Vcc of the previous stage. The drain of the equalizing transistor t
1
is connected to the node chg
1
which connects the first basic pump cell to a basic pump cell of a subsequent stage. With such an arrangement, the first basic pump cell functions as a switch for charging the node chg
1
so as to have a potential equal to that of the node N
1
. The source of the transistor s
1
of the first stage basic pump cell is connected to the node N
1
which connects the first basic pump cell to the power supply voltage Vcc of the previous stage. The drain of this transistor s
1
is connected to a gate of the equalizing transistor t
1
at a node trg
1
for charging the gate of the equalizing transistor t
1
. A capacitor c
1
of the first stage basic pump cell receives a clock signal CLK
1
at one of its electrodes. The other electrode of the capacitor c
1
is connected to a gate of the equalizing transistor t
1
at the node trg
1
for increasing the voltage at the gate of the equalizing transistor t
1
. Each basic pump cell of the other stages is connected to pump cells of previous and subsequent stages in a similar manner. An output-side node chgn of a basic pump cell of the last stage is connected to a source of a backflow preventing transistor te which prevents a backflow of an electric current. A gate of the backflow preventing transistor te is connected to a node N
2
which connects the basic pump cell of the last stage to the backflow preventing transistor te.
In the booster pump circuit having such a structure, in a voltage increasing operation, the clock signals CLK
1
and CLK
2
, which have opposite phases to each other as shown in
FIG. 5
, are input to the two capacitors c
1
and c
2
of the first basic pump cell. At the next stage, clock signals CLK
3
and CLK
4
, which have opposite phases to each other, and which have opposite phases to the voltages in the capacitors c
1
and c
2
of the previous basic pump cell as shown in
FIG. 5
, are input to the capacitors c
3
and c
4
.
At each of the following stages, a pair of capacitors respectively receive a pair of clock signals, which have opposite phases to each other, and which have also opposite phases to the voltages at a pair of capacitors of a previous basic pump cell. At the last stage, clock signals CLKm and CLKn are input to capacitors cm and cn of the basic pump cell. These clock signals CLK
1
through CLKn are generated by a known clock driving circuit (“Clock Driver” in FIG.
4
(
b
)). The clock driving circuit is controlled based on an activation signal (Pump Enable signal) which is used for activating a pump circuit.
For example, consider a case where power source voltage Vcc is input as an initial potential, and signals which vary between Vcc and Vss, such as clock signals shown in
FIG. 5
, are input as clock signals. When a clock signal CLK
2
is Vcc at a point A of
FIG. 5
, the voltage at the gate of the transistor s
1
is increased to Vcc due to the clock signal CLK
2
supplied through the capacitor c
2
so that the transistor s
1
is turned into a conductive state. As a result, the gate of the equalizing transistor t
1
(node trg
1
) is charged to Vcc.
Thereafter, the phases of the clock signals are inverted at a point B, so that the clock signal CLK
1
is transitioned to Vcc. The voltage of the node trg
1
is then increased to 2Vcc due to the clock signal CLK
1
supplied through the capacitor c
1
. As a result, the equalizing transistor t
1
is turned into a conductive state, so that the node chg
1
is charged with the initial potential Vcc, which is a potential difference between the node trg
1
and the node chg
1
.
Thereafter, the phases of the clock signals are inverted at a point C of
FIG. 5
, so that the clock signal CLK
1
is transitioned to Vss. As a result, the equalizing transistor t
1
is turned into a n
Morrison & Foerster / LLP
Nguyen Tan T.
Sharp Kabushiki Kaisha
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