Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-09-21
2001-10-23
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090
Reexamination Certificate
active
06307777
ABSTRACT:
TECHNICAL FIELD
The present invention relates the electrically writable and erasable non-volatile semiconductor storage device.
BACKGROUND OF THE INVENTION
So far EEPROM (electrically erasable and programmable ROM) has been used as one of the non-volatile semiconductor storage device.
FIG. 5
illustrates the reading of conventional EEPROM. The memory cell
116
consists of one selection transistor
117
and one storage transistor
118
which are connected to each other in serial. The drain of the selection transistor
117
is connected to the bit line BL, the source is formed commonly with the drain of the storage transistor
118
and the gate is connected to the word line WL. The storage transistor
118
has the floating gate and control gate, the control gate is connected to the control line CL and the source is connected to the common source line SS. The control line is connected to the sense line SL via the transistor
124
.
The storage transistor
118
stores information when the floating gate is electrified (at writing or erasing). The electric charge is poured into and extracted from the floating gate by the F-N (Fowler-Nordheim) current via a partial thin film (tunnel oxide film) between the floating gate and drain.
When the floating gate is electrified negatively, the threshold voltage (Vth) of the storage transistor increases. This state is referred to as the erasing state (the state “1”). On the other hand, the floating gate is electrified positively, the threshold voltage (Vth) of the storage transistor decreases. This state is referred to as the writing state (the state “0”).
At reading, the intermediate voltage (Vref) between the threshold voltage of the erasing state and that of the writing state is supplied to the sense line SL. If the word line WL is selected, the voltage of the sense line SL is impressed to the control line CL. If the state of the floating gate is “0”, a channel is formed between the source and the drain of the storage transistor
118
and then the storage transistor
118
becomes conductive. On the other hand, the state of the floating gate is “1”, a channel is not formed between the source and the drain of the storage transistor
118
and, therefore, the storage transistor
118
becomes nonconductive.
If the word line WL is selected, a specified current flows into the memory cell
116
according to the information stored in the storage transistor
118
because the selection transistor
117
has become conductive. The current is supplied to the memory cell
116
by the pull-up PMOS
126
via the bit line selection transistor
128
and the data line DL. The voltage of the data line DL, which depends on the specified current into the memory cell
116
and the current supplied by the pull-up PMOS
126
, is amplified and output by the sense amplifier (S. A.)
114
.
FIG. 6
is an electric characteristics diagram which illustrates an operation of the sense amplifier
114
. A stable voltage point of the data line DL is the intersections (d
1
and d
2
) of the current curves of the memory cells (the state “0” and the state “1”) and that of the pull-up PMOS
126
. A judgment voltage of the sense amplifier
114
is set at or around the center between the intersection (d
1
) when the state of the memory cell is “0” and the other intersection (d
2
) when the state of the memory cell is “1”. A data is judged as “0” if the voltage of the data line DL is lower than the judgment voltage and it is judged as “1” if such voltage of the data line DL is higher.
DISCLOSURE OF THE INVENTION
As described above, the conventional non-volatile semiconductor storage device selects one memory cell and reads the stored information.
The F-N current is used to store information in a memory cell as mentioned above and, therefore, high voltage must be impressed to the tunnel oxide film between the floating gate and drain. So, if writing and/or erasing are executed over and over again, due to the stress of high voltage, the tunnel oxide film is deteriorated and some of memory cells may be destroyed and short circuited. The quality of tunnel oxide films of such memory cells is worse than that of any other memory cells and, if even one of such memory cells is destroyed and short-circuited, the entire non-volatile semiconductor storage device becomes disabled. That is to say, the life time of non-volatile semiconductor storage depends on the worst memory cell. The quality of tunnel oxide film is affected by any defect or error in thin film arisen from the inconsistent conditions about forming of tunnel oxide film on a wafer or foreign substance mixed in the film.
FIG. 7
shows the short-circuited memory cell (defective memory cell) of which tunnel oxide film was destroyed. As shown in the electric characteristics diagram of
FIG. 6
, the current slightly higher than that of memory cell of the state “1” flows at or around the stable voltage point in the defective memory cell. Any data is judged as “1” always in such defective memory cell.
The purpose of the present invention is to extend the life of non-volatile semiconductor storage device and to offer the reliable non-volatile semiconductor storage device.
To solve the problem mentioned above, the invention in this application features that the first and second memory cells included in the several memory cells have the same information in the non-volatile semiconductor storage device in which the several memory cells are located in a direction of a row and in a direction of column, the information is read out by synthesizing the current into the first and second memory cells corresponding to the information stored in such first and second memory cells in the first mode and the control means to read out independently the information stored in the first and second memory cells is enabled in the second mode.
In the non-volatile semiconductor storage device of the present invention, the same information is stored in two memory cells (i.e., the first and second memory cells), the two memory cells are connected to each other in parallel (OR) in the first mode (at normal reading) and the current is synthesized according to the information in the memory cells (the state “0” or the state “1”). Even if the quality of the tunnel oxide film of the storage transistor in either of those two memory cells is poor and the floating gate and drain are short-circuited, the information can be read out correctly from the other memory cell. It is very rare that the quality of the tunnel oxide films of both two memory cells is poor. Therefore, the life of the non-volatile semiconductor storage device can be extended considerably
In the second mode (at test reading), the two memory cells are separated from each other so that those cells can operate independently to test those cells individually. This enables to screen the initial defective memory cells.
Moreover, the invention in this application features that, in the non-volatile semiconductor storage device mentioned above, the first memory cell and the second memory cell are connected to a common bit line and those memory cells are not adjoined. Otherwise, the invention in this application features that, in the non-volatile semiconductor storage device mentioned above, the first memory cell and the second memory cell are connected to a common word line and those memory cells are not adjoined.
Even if the quality of tunnel oxide film of either memory cell deteriorates considerably due to an error in the process conditions, the quality of tunnel oxide film of the other memory cell is hardly ever affected and the reliability of the non-volatile semiconductor storage device increases because two memory cells are separated from each other physically in the non-volatile semiconductor storage device of the present invention.
If those two memory cells are connected to a common bit line, the parasitic capacitance of the bit line in the first mode (at normal reading) and that of the bit line in the second mode (at test reading) are the same and, therefore, the difference between the reading conditions in suc
Katsuhara Noriaki
Tada Yoshihiro
Uenoyama Hiromi
Hogan & Hartson L.L.P.
Rohm & Co., Ltd.
Zarabian A.
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