Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-03-04
2008-03-04
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185240
Reexamination Certificate
active
11544608
ABSTRACT:
A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set to be different regions, a reading control circuit is constituted to carry out a reading operation by determining any of the divided regions which is to be read, selecting an optimum reading method and controlling the reading circuit based on the region information stored in the region information storage region, and an address which can be read in a short time in multivalued information stored in one memory cell is set to be a high speed reading region and is distinguished from regions having the other reading speeds. Consequently, it is possible to efficiently write and read information of 2 bits or more in one memory cell array without reducing a using efficiency of the memory cell array.
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Miyoshi Asako
Nakayama Masayoshi
Yamahira Seiji
Matsushita Electric - Industrial Co., Ltd.
Tran Michael T
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