Nonvolatile semiconductor memory with stabilized level shift cir

Details Nonvolatile semiconductor memory with stabilized level shift cir Nonvolatile semiconductor memory with stabilized level shift cir

1980-09-19

1984-04-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365104, 365184, 365185, G11C 1700, G11C 706, G11C 1140

Patent

active

044437188

ABSTRACT:
A nonvolatile semiconductor memory including a memory matrix having a plurality of memory cells with nonvolatile memory elements and arranged in the form of a matrix, a selecting circuit for selecting a desired memory cell from the memory matrix, and a read-out circuit for reading out the information stored in the selected memory cell. The read-out circuit includes a sense amplifier and an output buffer. The sensed amplifier includes an inverter having a load element to which a supply voltage is applied and a selected memory cell acting as a driver element. The output buffer includes a level shift circuit for shifting the level of an output signal voltage from the sense amplifier with the level shift circuit including a stabilizing circuit for stabilizing the level of the shifted signal voltage during fluctuations in the supply voltage. An output driver circuit is provided for receiving the shifted signal voltage from the level shift circuit.

REFERENCES:
patent: 3938108 (1976-02-01), Salsbury et al.
patent: 4082966 (1978-04-01), Lou
patent: 4179626 (1979-12-01), Oehler
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4287570 (1981-09-01), Stark
Kitano et al., "A 4-Mbit Full-Wafer Rom", IEEE Trans. on Electron Devices, vol. Ed-27, No. 8; 8/1980; pp. 1621-1628.
Wilson, "Cell Layout Boosts Speed of Low-Power 64K Rom", Electronics; pp. 96-99; 3/30/78.
Haug et al., "Programmable Read-Only Memory"; IBM Tech. Discl. Bull., vol. 18, No. 2, pp. 445-446; 7/1975.

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