Nonvolatile semiconductor memory with programming and erasing ve

Details Nonvolatile semiconductor memory with programming and erasing ve Nonvolatile semiconductor memory with programming and erasing ve

1999-04-08

2000-08-08

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518528, 36518518, G11C 1604

Patent

active

061011231

ABSTRACT:
Each memory cell of a nonvolatile semiconductor memory essentially consisting of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

REFERENCES:
patent: 5828600 (1998-10-01), Kato et al.

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