Nonvolatile semiconductor memory with improved sense...

Details Nonvolatile semiconductor memory with improved sense... Nonvolatile semiconductor memory with improved sense...

2002-03-22

2003-05-20

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230, C365S194000, C365S233500

Reexamination Certificate

active

06567310

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, and in particular to a nonvolatile semiconductor memory in which a method of driving core-side word lines and reference-side word lines is improved, to improve the sense amplifier operating margin.
2. Description of the Related Art
Flash memory is in widespread use as nonvolatile semiconductor memory. Memory cells comprise a cell transistor having a floating gate, and the fact that the threshold voltage of the cell transistor differs according to the amount of charge stored in the floating gate is utilized to perform data reading. That is, an amount of charge corresponding to the data is injected into the floating gate during programming, and this state is maintained. This state is maintained even if the power supply is turned off.
In readout, stored data is read by applying a prescribed read voltage to the control gate and detecting the drain current of the cell transistor. The threshold voltage of the cell transistor varies according to the amount of charge, and therefore the drain current of the cell transistor also differs according to the amount of charge. Accordingly, by detecting the value of the drain current, stored data can be read. More specifically, as described below, the drain current of the cell transistor is current-voltage converted, and the voltage value is detected by the sense amplifier.
Differences in the drain currents of cell transistors are minute, and so normally a reference level, obtained by current-voltage conversion of the drain current of a reference-side cell transistor, is compared with the core-side level. Here it is desirable that the sense amplifier which compares the two levels has a large operating margin.
FIG. 1
is a figure of the configuration of conventional nonvolatile memory;
FIG. 2
is a timing chart of its operation. Nonvolatile memory has a core-side memory cell array C-MCA which stores data, and a reference-side memory cell array R-MCA having comparison cells which are selected during read and verify processes.
The external address E-Add is supplied to the address buffer and ATD circuit
10
; when a change occurs in the external address at time t
0
, a detection signal ATD is generated. In response to this, a timing control circuit
12
generates a voltage-boost signal KICK, sense amplifier control signals EQ and LT, and other signals at a prescribed timing after time t
1
. The address buffer
10
supplies the pre-decoded X address X-Add to the X decoder
14
, and the Y address Y-add to the Y decoder
16
. Hence after the address change detection signal ATD has risen, the X decoder
14
operates to select the core-side word line C-WL and drive it to the power supply voltage Vcc.
When the core-side word line C-WL rises, the drain current of the cell MC flows at the core-side bit line C-BL, and the bit line current selected by the Y decoder
16
is supplied to the core-side cascode circuit
18
. The cascode circuit
18
converts the bit line current into the voltage SAI, which is supplied to the sense amplifier
26
.
The reference-side decoder
20
responds to the control signal KICK, selects the reference cell R-MC for reading, and passes a drain current for reference through the bit line R-BL. This bit line current is converted into a voltage by the reference-side cascode circuit
24
, and the voltage SAREF is supplied to the sense amplifier
26
.
In reading, the word lines C-WL and R-WL must be raised to a boost voltage Vbb which is higher than the power supply voltage Vcc. Hence the voltage-boost circuit
28
responds to the voltage-boost signal KICK occurring at time t
1
, and supplies the boost voltage Vbb to the word drivers of the decoders
14
,
20
, and puts both the word lines C-WL, R-WL at the boost voltage level Vbb. Accompanying this, the cell drain current value is determined, and the voltages SAI, SAREF converted by the cascode circuits
18
,
24
are also determined. Hence in the interval until the input voltages SAI, SAREF are determined, the output of the sense amplifier
26
is held in a neutral state by the equalizer signal EQ, and thereafter, in response to the latch signal LT, the detection level of the sense amplifier
26
is latched.
The pulse width of the address change detection signal ATD is set to an interval sufficiently long that the X decoder
14
operates after the address changes and the core-side word line C-WL is raised to the power supply voltage Vcc. This pulse width is also set such that redundancy judgment operation is completed and the boost voltage level Vbb, which has fallen due to the boosting-voltage operation of the previous read cycle, can recover sufficiently. The pulse width of the address change detection signal ATD tends to become longer when skew occurs in the external address E-Add. Skew in the address signal also tends to cause the decoder operation time to be lengthened, and this is accompanied by a lag in the timing with which the voltage in the core-side word line C-WL rises.
The voltage-boost signal KICK is a control signal to raise the word lines C-WL and R-WL to the high level Vbb while at H level. During this interval, while the equalizer signal EQ is at H level, the sense amplifier
26
detects the voltage difference of the two inputs SAI and SAREF, and the detection signal is latched by the latch signal LT. Hence simultaneously with falling of the latch signal LT, the voltage-boost signal KICK falls, and the voltages in the word lines C-WL, R-WL fall.
FIG. 3
is a timing chart of operation when skew occurs in the Y address in FIG.
2
. In this example, of the external addresses E-Add, skew does not occur on the X-address side, but does occur on the Y-address side. As the X address changes without skew, operation of the X decoder
14
at a prescribed time after the time t
0
at which the address change detection signal ATD rises, causes the core-side word line C-WL to rise to the power supply voltage Vcc.
On the other hand, skew occurring in the Y address is accompanied by a lengthening of the pulse width of the address change detection signal ATD, and there is a lag in the falling edge at time t
1
. Hence the boosting operation of the core-side word line C-WL and the rising operation of the reference-side word line R-WL are also delayed considerably.
As shown in
FIGS. 2 and 3
, the timing of the rising edge of the core-side word line C-WL differs from the timing of the rising edge of the reference-side word line R-WL, and so a time difference occurs in the waveform changes of the sense amplifier inputs SAI and SAREF, which change in response to these rising edges. This time difference gives rise to a period in which the operating margin of the sense amplifier is reduced; and in order to prevent erroneous operation caused by this, the pulse width of the equalizer pulse EQ which controls the sense amplifier detection period must be made long. This means that the access time is delayed. Also, when the pulse width of the equalizer pulse EQ is narrow, erroneous operation of the sense amplifier is prone to occur.
FIG. 4
is a figure which explains erroneous operation of the sense amplifier.
FIG. 4A
shows changes in the core-side word line and reference-side word line, and in inputs to the sense amplifier SAI(
0
), SAI(
1
), SAREF, plotted against time on the horizontal axis.
FIG. 4B
shows changes with time in the core-side cell currents Ic(
0
), Ic(
1
) and the reference-side cell current Ir.
Assume the worst case for data “0”s and “1”s, and suppose that a data “0” cell with a high threshold is positioned close to the X decoder, and a data “1” cell with a low threshold is positioned farthest from the X decoder. In this case, the rising waveforms of the word lines C-WL(
0
), C-WL(
1
) for each of these cells are as shown in FIG.
4
A. That is, the rise of the word line C-WL(
1
) lags somewhat. Together with this, the cell currents Ic(
0
) and Ic(
1
) rise with the timing of time t
1
, at which the word line levels are raised to the boost voltage level Vbb.

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