Nonvolatile semiconductor memory well voltage setting...

Details Nonvolatile semiconductor memory well voltage setting... Nonvolatile semiconductor memory well voltage setting...

2002-02-27

2003-04-15

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185270, C365S185290, C365S185330

Reexamination Certificate

active

06549465

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a well voltage setting circuit for erasing a nonvolatile semiconductor memory and, in particular, to a nonvolatile semiconductor memory well voltage setting circuit capable of preventing latch-up during erase of a nonvolatile semiconductor memory that uses a channel erase system and a semiconductor memory device provided with the circuit.
Conventionally, there has been an ETOX (registered trademark of Intel) type flash memory cell as a flash memory used most generally.
FIG. 12
shows a schematic sectional view of this ETOX type flash memory cell. In this ETOX type flash memory cell, a floating gate
103
is formed on a substrate
108
located between a source
106
and a drain
107
via a tunnel oxide film
105
, and a control gate
101
is further formed via a layer insulation film
102
.
The principle of operation of this ETOX type flash memory cell will be described next. In this memory cell, according to voltage conditions shown in Table 1, during write, a voltage Vpp (10 V, for example) is applied to the control gate
101
, a reference voltage Vss (0 V, for example) is applied to the source
106
, and a voltage of 6 V is applied to the drain
107
.
TABLE 1
Application Voltages in Conventional Modes
Control Gate
Drain
Source
Substrate
Write
10 V
6 V/0 V
0 V
0 V
Erase
−9 V
Open
4 V
0 V
Read
 5 V
1 V
0 V
0 V
With this arrangement, a large amount of current flows through the channel region to generate hot electrons in a portion on the drain side where the electric field is high. The electrons are injected into the floating gate
103
to raise a threshold voltage of this memory cell. The distribution state of the raised threshold voltage is shown in FIG.
13
. In
FIG. 13
, the vertical axis represents the number N of memory cells, and the horizontal axis represents the threshold voltage of the memory cells.
In erase operation, a voltage Vnn (−9 V, for example) is applied to the control gate
101
, and a voltage Vpe (4 V, for example) is applied to the source
106
, so as to extract electrons from the floating gate
103
on the source side. Consequently, the threshold voltage of the memory cell is lowered.
FIG. 13
also shows the distribution state of the lowered threshold voltage. In this erase operation, a BTBT (Band To Band Tunneling) current flows. Concurrently, hot holes and hot electrons are generated. The hot electrons flow toward the substrate
108
. On the other hand, the hot holes are pulled toward the tunnel oxide film
105
to be trapped in the tunnel oxide film
105
. This trapping phenomenon degrades reliability.
In read operation of the memory cell, a voltage of 1 V is applied to the drain
107
, and a voltage of 5 V is applied to the control gate
101
. In this case, when this memory cell is in the erased state, that is, when the threshold voltage is low, a current flows through the cell. By this, the storage information is determined to be “1”. When this memory cell is in the programmed state, that is, when the threshold voltage is high, no current flows through the memory cell. By this, the storage information is determined to be “0”.
In the ETOX type flash memory cell, as described above, there is a problem that the BTBT current generated on the source side in the erase operation deteriorates the reliability of the memory cell.
As a means for solving this problem, there is a method for using channel erase that causes no BTBT current during the erase operation. This method is disclosed in Japanese Patent Laid-Open Publication No. HEI 11-39890. The write and read operations of this method are similar to those of the aforementioned source side erase system.
FIG. 14
shows the operational principle of this channel erase system. As shown in
FIG. 14
, in erase operation, a voltage Vnn (−9 V, for example) is applied to a word line connected to a control gate
191
on a layer insulation film
192
, and a voltage Vesc (+6 V, for example) is applied to a source
195
and a well
197
. The source
195
may be in an OPEN state. By this operation, an intense electric field is applied to a tunnel oxide film
194
located between the channel layer and the floating gate
193
, so that electrons are extracted from the floating gate
193
by the FN (Fowler-Nordheim) tunneling phenomenon and the threshold value are lowered. The following Table 2 shows the voltage application conditions in this case.
TABLE 2
Application Voltages in Conventional Modes
Control Gate
Drain
Source
Substrate
Write
10 V
6 V/0 V
0 V
0 V
Erase
−9 V
Open
6 V or Open
6 V
Read
 5 V
1 V
0 V
0 V
At this time, a potential (Vp-well) of the well
197
is equal to that of the source
195
, and therefore, no electric field is concentrated on a boundary portion between the source
195
and the well
197
, so that no BTBT current is generated. Consequently, no hot hole is generated. Therefore, trap of hot holes does not occur in the tunnel oxide film
194
, so that the reliability of the memory cell is improved.
Next,
FIG. 15
shows in more detail a structural cross-sectional view of the memory cell in which the channel erase system shown in
FIG. 14
is put into practice. This structure is called the triple well structure, wherein an N-well
209
is provided so as to electrically separate a substrate
208
from a P-well
204
in which the memory cell is formed.
In this case, a reference voltage (0 V, for example) is applied to the P-substrate
208
so as to put a bit line BL connected to the drain
207
into a floating state. A voltage Vesc (6 V, for example) is further applied to a line CA connected to a contact region
205
connected to the source
206
so as to apply the voltage Vesc to the P-well
204
. The common source line CS is a line for commonly connecting together the sources in a block.
Further, a voltage Vnn (−9 V, for example) is applied to a control gate
201
via the word line WL connected to the control gate
201
, and a voltage Vnw (not lower than 6 V, for example) is applied to the N-well
209
.
By this operation, the source
206
and the P-well
204
are made to have same potential, effecting channel erase.
In
FIG. 15
, the region denoted by the symbol N is an N
+
diffusion region and represents a contact region for electrical connection to the N-well
209
. Moreover, in
FIG. 15
, the region denoted by the symbol P is a P
+
diffusion region and represents a contact region for electrical connection to the P-well
204
.
During erase (also, write and during operations), as drive circuits (drivers) for applying the aforementioned various voltages, there are provided a word line drive circuit for driving the word line WL, a bit line drive circuit for driving the bit line BL, a common source line drive circuit for driving the common source line, an N-well drive circuit and a P-well drive circuit, which are arranged in the peripheral portion of the memory cell array.
Further, in order to supply various voltages to these drive circuits, there are arranged a positive voltage charge pump circuit for generating a positive high voltage from a power voltage through boosting, a negative voltage charge pump circuit for generating oppositely a negative high voltage from the power voltage through boosting, regulator circuits for generating various voltages by deboosting inputs outputted from these charge pump circuits, stabilizing those voltages and outputting the voltages, and so on.
FIG. 16
shows a construction necessary for, in particular, erase among the peripheral circuits of the memory cell array.
FIG. 17
shows one block of 64 KB of the memory cell array. These memory cells are formed in one P-well (see FIG.
18
).
As shown in
FIG. 17
, the memory cell array of one block is constructed by a plurality of memory cells MS arranged on the array. The control gates of 512 memory cells MS are connected to this word line WL
0
, as in the cases with the word lines WL
1
through WL
1023
.
The drains of 1024 memory cells MS are connected to the bit line BL
0
, as in the c

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