Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-05-27
2008-05-27
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290
Reexamination Certificate
active
11401418
ABSTRACT:
A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.
REFERENCES:
patent: 6134149 (2000-10-01), Lin
patent: 6404683 (2002-06-01), Yumoto
patent: 6553510 (2003-04-01), Pekny
patent: 6850436 (2005-02-01), Ogawa
patent: 6868032 (2005-03-01), Kozakai et al.
patent: 7116603 (2006-10-01), Kanda et al.
patent: 2002/0051394 (2002-05-01), Tobita et al.
patent: 2005/0190615 (2005-09-01), Linde et al.
patent: 2000-57795 (2000-02-01), None
Kasai Takamichi
Kato Hideo
Hoang Huan
Kabushiki Kaisha Toshiba
Tran Anthan T
LandOfFree
Nonvolatile semiconductor memory including redundant cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory including redundant cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory including redundant cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3956424