Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2011-04-12
2011-04-12
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185230, C365S185270, C365S185280
Reexamination Certificate
active
07924620
ABSTRACT:
A nonvolatile semiconductor memory includes a transistor, a first MOS, a second MOS, a first voltage circuit, and a second voltage circuit. The transistor includes a accumulation layer, a control gate, and a first impurity diffused layer. The first MOS includes a first electrode and a second layer. The second MOS includes a second electrode and a third layer, after the channels being formed, the first MOS and the second MOS being cut off. The first voltage circuit applies a first voltage to an active region to generate a forward bias. The second voltage circuit applies a second voltage, and a third voltage to the control gate of the transistor, after the first voltage circuit charges the first to third impurity diffused layer to the first voltage, the second voltage circuit applying the second voltage and the third voltage to the control gate of the transistor.
REFERENCES:
patent: 5414665 (1995-05-01), Kodama
patent: 7009881 (2006-03-01), Noguchi
patent: 7738298 (2010-06-01), Chae et al.
patent: 2002-245785 (2002-08-01), None
patent: 2007-226897 (2007-09-01), None
patent: 2008-204545 (2008-09-01), None
Kabushiki Kaisha Toshiba
Nguyen Tan T.
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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