Nonvolatile semiconductor memory having three-level memory...

Details Nonvolatile semiconductor memory having three-level memory... Nonvolatile semiconductor memory having three-level memory...

2005-01-25

2005-01-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185200, C365S185240, C365S185330, C365S185220

Reexamination Certificate

active

06847550

ABSTRACT:
A memory uses multiple threshold levels in a memory cell that are not a power of two, and further uses a cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the voltage margin for the three-level memory cells is larger that the voltage margin available in the commonly used four-level memory cells. This increased voltage margin facilitates memory cell threshold voltage sensing, thereby increasing the reliability of the memory. Memory reliability may be further improved by increasing the voltage margin between the memory cell0state and the1state relative to the voltage margin between the1state and the2state, which more effectively accommodates charge loss from the0state through electron leakage. Asymmetrical read and program mapping may also be used to improve read reliability in the presence of ground noise or VCCnoise.

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