Nonvolatile semiconductor memory having an address-transition-de

Details Nonvolatile semiconductor memory having an address-transition-de Nonvolatile semiconductor memory having an address-transition-de

1994-01-03

1995-06-27

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365201, 365203, 365226, G11C 700

Patent

active

054285801

ABSTRACT:
The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power. A nonvolatile semiconductor memory in which, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level V2, which is lower than an applied voltage for a normal read operation, or a voltage at a second verification level V3, which is higher than the applied voltage V1, the nonvolatile semiconductor memory comprising: an address-transition-detection circuit 1; a supply voltage detection circuit 3 for generating an initialization transition signal at the rise of a supply voltage when the supply voltage has reached a first supply voltage transition threshold level V4 higher than the first verification level V2; and a transition operation circuit 2 for performing operations such as bit line charge-up in accordance with the address transition signal and initialization transition signal.

REFERENCES:
patent: 4633442 (1986-12-01), Borghese
patent: 4972374 (1990-11-01), Wang et al.
patent: 5079744 (1992-01-01), Tobita et al.

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