Nonvolatile semiconductor memory having a stress relaxing voltag

Details Nonvolatile semiconductor memory having a stress relaxing voltag Nonvolatile semiconductor memory having a stress relaxing voltag

1997-03-03

1998-07-28

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Disturbance control

36518514, 36518518, 36518523, 36518531, G11C 1606

Patent

active

057870349

ABSTRACT:
A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

REFERENCES:
patent: 4466081 (1984-08-01), Masuoka
patent: 5034926 (1991-07-01), Taura et al.
patent: 5289425 (1994-02-01), Horiguchi et al.
Asano et al., English Translation of JP 64-059698, pp. 1-16 (1989).

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