Nonvolatile semiconductor memory for positively holding stored d

Details Nonvolatile semiconductor memory for positively holding stored d Nonvolatile semiconductor memory for positively holding stored d

1993-12-01

1996-05-21

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518512, G11C 1134

Patent

active

055196527

ABSTRACT:
A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory for positively holding stored d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory for positively holding stored d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory for positively holding stored d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2044245