Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2005-01-18
2005-01-18
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S185210, C365S185230
Reexamination Certificate
active
06845042
ABSTRACT:
A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
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K.-D. Suh, et al., IEEE Journal of Solid State Circuits, vol. 30, No. 11, pp. 1149-1156, “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, Nov. 1995.
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Hashimoto Koji
Ichige Masayuki
Kuji Tatsuaki
Mori Seiichi
Sakui Koji
Ho Hoai
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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