Nonvolatile semiconductor memory device with soft-programming to

Static information storage and retrieval – Floating gate – Multiple values

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Details

36518517, 36518522, G11C 1604

Patent

active

061341401

ABSTRACT:
A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

REFERENCES:
patent: 5652719 (1997-07-01), Tanaka et al.
patent: 5805501 (1998-09-01), Shiau et al.
patent: 5870334 (1999-02-01), Hemink et al.
Tae-Sung Jung et al., "A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications"; IISSC Digest of Technical Papers; Feb. 1996; pp. 32-33.

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