Nonvolatile semiconductor memory device with selective tow erasu

Details Nonvolatile semiconductor memory device with selective tow erasu Nonvolatile semiconductor memory device with selective tow erasu

1992-10-13

1994-05-24

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36523003, 36523008, 365900, 257315, G11C 700

Patent

active

053155475

ABSTRACT:
In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.

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