Nonvolatile semiconductor memory device with reduced variation i

Details Nonvolatile semiconductor memory device with reduced variation i Nonvolatile semiconductor memory device with reduced variation i

1991-09-25

1993-01-26

Sniezek, Andrew L.

Static information storage and retrieval

Floating gate

Particular biasing

365204, 36523006, G11C 1134

Patent

active

051827255

ABSTRACT:
In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 4404659 (1983-09-01), Kihara et al.
patent: 4638459 (1987-01-01), Pechar et al.
Van Buskirk et al, "E-PROMs Graduate to 256-K Density with Scaled n-channel Process", Electronics (Feb. 24, 1983), pp. 4-113-4-117.
Esquivel et al, "High Density Contactless, Self-Aligned EPROM Cell Array Technology", IEDM (1986), pp. 592-595.

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