Nonvolatile semiconductor memory device with NAND cell structure

Details Nonvolatile semiconductor memory device with NAND cell structure Nonvolatile semiconductor memory device with NAND cell structure

1993-05-26

1995-03-21

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 36518911, 36523006, 3652335, G11C 700

Patent

active

054002796

ABSTRACT:
An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or "L" level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or "H" level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The "H" level of the voltage signal is higher than the power supply voltage and yet lower than a normal "H" level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.

REFERENCES:
Masuoka et al. "New Ultra High Density EEPROM and Flash EEPROM with NAND Structure Cell", IEDM Technical Digest, Dec. 6-9, 1987, pp. 552-555.
Shirota et al. "A New NAND Cell for Ultra High Density 5V-Only EEPROM," VLSI Research Center. Adler, Density Arrayed EEPROM Having Low Voltage Tunnel Write, IBM Tech. Disclosure Bulletin, vol. 27, No. 6, Nov. 84 pp. 3302-3307.

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