Nonvolatile semiconductor memory device with MOS transistors...

Details Nonvolatile semiconductor memory device with MOS transistors... Nonvolatile semiconductor memory device with MOS transistors...

2005-11-01

2005-11-01

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010

Reexamination Certificate

active

06961268

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, word lines, select gate lines, first and second row decoders, and a control circuit. The memory cell includes a first MOS transistor with a stacked gate formed on a first well region and a second MOS transistor having a drain connected to a source of the first MOS transistor. The word line connects in common control gates of the first MOS transistors. The select gate line connects in common gates of the second MOS transistors. The first row decoder in a write operation, applies a positive and negative potentials to the selected word line and the first well region, respectively and after the write operation, brings the selected word line and the first well region into a floating state. The control circuit short-circuits the selected word line and first well region in the floating state.

REFERENCES:
patent: 5592001 (1997-01-01), Asano
patent: 6222774 (2001-04-01), Tanzawa et al.
patent: 6373749 (2002-04-01), Atsumi et al.
patent: 2004/0212008 (2004-10-01), Hasegawa
Wei-Hua Liu et al, “A2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications,” Non-volatile Semiconductor Workshop 4.1, Feb. 1997.

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