Nonvolatile semiconductor memory device with improved...

Details Nonvolatile semiconductor memory device with improved... Nonvolatile semiconductor memory device with improved...

2000-10-25

2002-05-14

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185200, C365S185290

Reexamination Certificate

active

06388921

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a nonvolatile semiconductor memory device, enabling electrical programming/erasing of data and storage of information even when the power is off.
2. Description of the Background Art
In resent years, digital communication networks using portable information communication terminals such as a cellular phone or Internet have been developed, and nonvolatile semiconductor memory devices are widely used in such portable terminals as memory devices enabling nonvolatile storage of information.
One example of such nonvolatile semiconductor memory devices is an electrically programmable flash memory in which stored data can be electrically erased collectively for a group of a predetermined number of bits.
FIG. 9
is a schematic block diagram showing a configuration of a conventional nonvolatile semiconductor memory device
100
.
Referring to
FIG. 9
, nonvolatile semiconductor memory device
100
includes a ROM (Read Only Memory) therein, a CPU
8
for controlling programming and erasing operations in response to a program code held in the ROM and a command signal applied from an external source, a high voltage generating circuit for programming/erasing
10
for generating a high voltage for programming and erasing from an external power potential (not shown), and a memory cell array
120
.
Memory cell array
120
includes memory blocks
120
-
1
to
120
-n formed in P wells electrically separated from one another. The erasing operation of nonvolatile semiconductor device
100
is performed for each of the memory blocks
120
-
1
to
120
-n.
Nonvolatile semiconductor memory device
100
further includes an input buffer
2
for receiving from an external source an address signal ADD, a chip enable signal/CE, an output enable signal/OE, a write enable signal/WE and a reset signal/RP, WP input buffer
4
for receiving a write protect signal/WP from an external source, a WL decoder/WL driver
14
for selecting a memory block and a word line in response to a row address signal applied from input buffer
2
, a data buffer
6
for transmitting/receiving a data signal DATA to/from an external source, a BL decoder/driver
16
for selecting a bit line in response to a column address applied from input buffer
2
to transmit/receive data between the selected bit line and data buffer
6
, and a sense amplifier circuit
18
for reading data by detecting current flowing in the bit line at the time of a reading operation.
Memory block
120
-
1
includes a memory transistor MT for storing normal data arranged in rows and columns and a memory transistor MTL for lock bit holding information for protecting memory block
120
-
1
from programming/erasing.
Memory block
120
-
1
further includes a selector gate SG activated when memory block
120
-
1
is selected, to connect a main bit line MBLO with a sub bit line SBL.
Nonvolatile semiconductor memory device
100
is so-called NOR flash memory, the source of each memory transistor MT being connected to a common source line SL.
Nonvolatile semiconductor memory device
100
further includes a SL driver
12
for receiving a predetermined potential from high voltage generating circuit for programming/erasing
10
to set the potential of source line SL.
Sense amplifier circuit
18
includes sense amplifiers SA
0
to SAn corresponding to respective bit lines, and a sense amplifier SAL for detecting current in main bit line MBLL to which lock bit memory transistor MTL is connected. Sense amplifier SAL outputs the result of the detected current to CPU
8
, which determines, according to the output of sense amplifier SAL, whether the programming or erasing operation is performed for each of memory blocks
120
-
1
to
120
-n.
Lock bit memory transistor MTL is a nonvolatile memory transistor with a floating gate, which is rewritable by an operation similar to that of normal data memory transistor MT. The state of lock bit memory transistor MTL defines whether a block may be subject to data rewriting, to provide a function of protecting the block from rewriting of data already programmed therein even when an instruction for data rewriting is executed.
Operations of a memory cell, i.e., the cell holding normal data, and a lock bit cell, i.e., the cell holding a lock bit, are described below by means of NOR memory for example.
FIG. 10
is a schematic illustrating a programming operation to a memory cell.
Referring to
FIG. 10
, a word line WL
0
is set to 10V while word lines WL
1
-WL
3
are set to 0V. A sub bit line SBL
1
is set to 5V while a sub bit line SBL
0
is set to 0V. A well in which a memory block to be programmed is formed is set to 0V and source line SL is also set to 0V.
Such settings allow a memory transistor connected to word line WL
0
and sub bit line SBL
1
to be selected. Electrons are injected into the floating gate of the selected memory transistor so that data “0” is held therein.
FIG. 11
is a schematic section view illustrating a programming operation to the selected cell in FIG.
10
.
Referring to
FIG. 11
, a positive high voltage of approximately 10V is applied to word line WL and a positive voltage of approximately 5V is applied to sub bit line SBL, and the potentials of the P well and source line SL are set to 0V for electrons to be injected into the floating gate F from the P well and source S. The injection of electrons varies a threshold voltage Vth of the selected memory transistor to be approximately 6V or higher. This is called the programming operation.
For convenience of description, the impurity region connected to source line SL is referred to as source S and the impurity region opposite to source S with a channel region interposed therebetween is referred to as drain D.
FIG. 12
is a schematic circuit diagram illustrating a reading operation.
Referring to
FIG. 12
, word line WL
0
is set to 3V, word lines WL
1
-WL
3
are set to 0V and source line SL is set to 0V. The reading operation is performed by a sense amplifier connected to the sub bit line, determining whether current flows in the selected memory transistor to which word line WL
0
is connected.
If the selected memory cell is in a programmed state, i.e., the state in which the threshold voltage Vth is higher than 6V, no current flows therein, which is recognized that data “0” is held in the selected cell. On the other hand, if the threshold voltage of the selected transistor is low, i.e., if the threshold voltage Vth is in a range of approximately 1-3V, current flows in the current path shown with a broken line in FIG.
12
. In this case, it is recognized that data “1” is held in the memory transistor.
FIG. 13
is a schematic section view illustrating an operation of the selected memory transistor at the time of reading.
Referring to
FIG. 13
, gate G of the memory transistor is connected to word line WL and set to 3.0V. The drain D and source S of the memory transistor are respectively connected to sub bit line SBL and source line SL, the drain being set to 1.0V while the source being set to 0V. The potential of P well in which the memory transistor is formed is set to 0V. If electrons are injected into floating gate F and the threshold voltage Vth exceeds 6.0V, the memory transistor of the selected cell is not turned on even when the gate potential is 3.0V, avoiding current flowing from drain D to source S.
On the other hand, if only few electrons are injected into the floating gate F and the threshold voltage Vth is lower than 3.0V, current i flows from drain D to source S. The current i is detected by the sense amplifier connected to the sub bit line SBL, for reading the information in the selected cell.
FIG. 14
is a schematic circuit diagram illustrating an erasing operation of a memory cell.
Referring to
FIG. 14
, when the erasing operation is performed, word lines WL
0
-WL
3
of the block to be subjected to the erasing operation are collectively set to −10V, while the potential of the well in which the memory block to be subjected to the erasing operatio

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