Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-05-29
2007-05-29
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185210
Reexamination Certificate
active
11183032
ABSTRACT:
A nonvolatile semiconductor memory device is provided comprising a plurality of memory cell arrays, each of which consists mainly of sidewall type memory cells arranged in a matrix, the memory cell having a MOSFET structure where memory functional element for holding charges are provided on both sides of a gate electrode. The memory cell array is divided into sectors. The memory device further comprises a sector selecting circuit for, when one of the memory cell arrays is to be erased collectively, sequentially selecting at most a predetermined number of the sectors at a time from the memory cell array to be erased, and an erase voltage applying circuit for, when the collective erasing action is carried out, applying a predetermined level of erasing voltage to the sectors selected at once by the sector selecting circuit.
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Graham Kretelia
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Zarabian Amir
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