Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-05-31
2005-05-31
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189030, C365S210130
Reexamination Certificate
active
06901025
ABSTRACT:
In a read operation, for example, 32 sense amplifiers read 32 pieces of data in a group. After that, the read data is outputted on a 4-bit unit basis. A memory cell array operates at a low frequency which is ⅛ of an actual data output frequency. On the other hand, in a write operation, data is transferred from the outside to a semiconductor memory device bit by bit every cycle. Consequently, by providing a number of latches of a pipeline in a write access path, the writing operation is enabled even at a high frequency. Specifically, at the time of reading, a memory array operates at a low frequency which is ⅛ of a data output frequency. At the time of writing, data is written every clock.
REFERENCES:
patent: 6347056 (2002-02-01), Ledford et al.
patent: 6392957 (2002-05-01), Shubat et al.
patent: 6643204 (2003-11-01), Agrawal
patent: 5-342118 (1993-12-01), None
Elms Richard
Luu Pho M.
Renesas Technology Corp.
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