Nonvolatile semiconductor memory device using a bit line potenti

Details Nonvolatile semiconductor memory device using a bit line potenti Nonvolatile semiconductor memory device using a bit line potenti

1998-10-07

1999-12-21

Tran, Andrew

Static information storage and retrieval

Floating gate

Disturbance control

36518517, 36518521, 36518525, G11C 1606

Patent

active

060058021

ABSTRACT:
A nonvolatile semiconductor memory device includes a memory cell section including at least one nonvolatile memory cell, a first bit line connected to one end of the memory cell section, and a second bit line capacitively coupled with the first bit line. At the data programming time, the first bit line is set to a first voltage, thereafter rendered electrically floating, the voltage of the second bit line is changed to a second voltage after the first bit line is rendered electrically floating, and then the first bit line which is set in the electrically floating state is capacitively coupled with second bit line to change the voltage of the first bit line to a third voltage higher than the first and second voltages.

REFERENCES:
patent: 5379256 (1995-01-01), Tanaka et al.
"A 3.3 V 32 Mb NAND Flash Memory", Kang-Deog Suh et al.; IEEE International Solid-State Circuits Conference; 1995; pp. 128-129.
"A 35ns-Cycle-Time 3.3 V Only 32 Mb NAND Flash EEPROM", Kenichi Imamiya et al.; IEEE International Solid-State Circuits Conference; 1995 pp. 130-131.
IEDM 97, "A Triple Polysilicon Stacked Flash Memory Cell with Self-Booosting Programming", Jung Dal Choi et al, pp. 285-286.

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