Nonvolatile semiconductor memory device that can suppress...

Details Nonvolatile semiconductor memory device that can suppress... Nonvolatile semiconductor memory device that can suppress...

2005-03-22

2005-03-22

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185330

Reexamination Certificate

active

06870771

ABSTRACT:
In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.

REFERENCES:
patent: 5297096 (1994-03-01), Terada et al.
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 5793678 (1998-08-01), Kato et al.
patent: 5920508 (1999-07-01), Miyakawa et al.

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