Nonvolatile semiconductor memory device that achieves...

Details Nonvolatile semiconductor memory device that achieves... Nonvolatile semiconductor memory device that achieves...

2008-05-27

2008-05-27

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185130

Reexamination Certificate

active

07379345

ABSTRACT:
A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.

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Hiraki et al., “MP 6.8 A3.3V 90MHz Flash Memory Module Embedded in a 32b RISC Microcontroller”, ISSCC99, pp. 116-117.

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