Nonvolatile semiconductor memory device storing multi-bit data

Static information storage and retrieval – Floating gate – Multiple values

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36518521, G11C 1604

Patent

active

061377198

ABSTRACT:
A data latch circuit group latches data read by a sense latch circuit group when a read voltage is supplied to a word line. These data are transferred to a read data conversion circuit and converted to 2-bit data. Thus, no operation processing may be performed through a bit line or a transistor in a memory cell array, whereby a read time can be reduced for reducing power consumption.

REFERENCES:
patent: 5530955 (1996-06-01), Kaneko
patent: 5969985 (1999-10-01), Tanaka et al.
patent: 5982667 (1999-11-01), Jyouno et al.
patent: 6026014 (2000-02-01), Sato et al.
"A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Applications", A. Nozoe et al., ISSCC 1999, Digest of Technical Papers, pp. 110-111.

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