Nonvolatile semiconductor memory device operable at high speed w

Details Nonvolatile semiconductor memory device operable at high speed w Nonvolatile semiconductor memory device operable at high speed w

1998-03-03

1999-11-02

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518526, 36518529, G11C 1604

Patent

active

059782641

ABSTRACT:
A memory cell transistor connects its drain with a corresponding subbit line. In a program operation, a selected subbit line is connected to a program main bit line. In a read operation, a selected subbit line is connected with the base of a bipolar transistor, so that a channel current of a selected memory cell transistor flows as a base current. The bipolar transistor amplifies this base current, and controls a current flowing through a read main bit line.

REFERENCES:
patent: 5483483 (1996-01-01), Choi et al.
patent: 5590072 (1996-12-01), Choi
patent: 5659505 (1997-08-01), Kobayashi et al.
patent: 5818761 (1998-10-01), Onakado et al.
"A Novel NAND Structure with a BJT Contact for the High Density Mask ROMs" Choi, et al., 1994 Symposium on VLSI, Technology Digest of Technical Papers, pp. 163-164.

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