Static information storage and retrieval – Floating gate – Data security
Reexamination Certificate
2002-10-04
2004-03-23
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Data security
C365S195000
Reexamination Certificate
active
06711055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device provided with a data protection function based on the use of passwords.
2. Description of the Related Art
In nonvolatile semiconductor memory devices of a dual-operation type, a memory cell array is divided into four banks, for example, and a read operation can be performed on a selected bank while a rewrite operation (program-&-erase operation) is being performed on another bank.
FIG. 1
is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device of a dual-operation type.
A nonvolatile semiconductor memory device
10
includes a command register
11
, a command decoder
12
, a control circuit
13
, a latch-signal generation circuit
14
, a bank decoder
15
, a bank control circuit
16
, a bank-A selection circuit
17
, a bank-B selection circuit
18
, a bank-C selection circuit
19
, a bank-D selection circuit
20
, a bank-A
21
, a bank-B
22
, a bank-C
23
, and a bank-D
24
.
The command register
11
receives command signals and control signals from an exterior of the device, and supplies them to the command decoder
12
. The command decoder
12
decodes the commands, and supplies the decoded commands to the control circuit
13
and the bank control circuit
16
. The control circuit
13
is a state machine that controls internal circuitry of the nonvolatile semiconductor memory device
10
based on the decoded commands supplied thereto.
The latch-signal generation circuit
14
generates a latch signal X in response to a chip-enable signal /CE or a write-enable signal /WE, and supplies the latch signal X to the bank selection circuits
17
through
20
. The bank decoder
15
decodes a bank address supplied from the exterior of the device. The bank decoder
15
generates bank selection signals APBK, BPBK, CPBK, and DPBK for selecting respective banks according to the decoded bank address, and supplies them to the bank selection circuits
17
through
20
. The bank selection circuits
17
through
20
generate signals ordering write operations and signals ordering read operations with respect to the respective banks
21
through
24
. For example, the bank-A selection circuit
17
asserts a signal ABRSEL instructing the bank-A
21
to perform a read operation or a signal ABWSEL instructing the bank-A
21
to perform a write operation. Each of the banks
21
through
24
is provided with a memory cell array, an address decoder, and a control circuit, and carries out an operation selected from the write operation and the read operation.
The bank control circuit
16
receives a signal Z from the command decoder
12
indicative of receipt of a write command, and responds to this signal Z by supplying a read/write-selection signal Y for ordering a write operation to the bank selection circuits
17
through
20
. If the entered bank address indicates the bank-A
21
, for example, the bank decoder
15
asserts a signal APBK. With the bank selection signal APBK being asserted by the bank decoder
15
, the bank-A selection circuit
17
latches a bank-selection state indicative of the selected status of the bank-A
21
in response to the latch signal X from the latch-signal generation circuit
14
. Based on the latched bank selection state and the read/write-selection signal Y indicative of a write operation, the bank-A selection circuit
17
performs a write operation on the bank-A
21
. In response, the bank-A
21
carries out a write operation.
Consideration will now be given to a particular situation in which the bank-A
21
is undergoing a write operation when a read command is entered into the command register
11
as a next command from the exterior, and a read bank address is input into the bank decoder
15
. In response to the read command, the read/write-selection signal Y turns into a signal state indicative of a read operation. If the bank address indicates the bank-B
22
, for example, the bank decoder
15
will asserts the bank selection signal BPBK. In response to the bank selection signal BPBK selecting the bank-B
22
and the read/write-selection signal Y indicative of a read operation, the bank-B selection circuit
18
instructs the bank-B
22
to perform a read operation. In response, the bank-B
22
carries out a read operation. When this happens, the write operation of the bank-A
21
continues to be performed concurrently with the read operation of the bank-B
22
.
As described above, a nonvolatile semiconductor memory device of a dual-operation type can perform a read operation on a selected bank while performing a write operation (program-&-erase operation) on another bank.
Some of the nonvolatile semiconductor memory devices of today are provided with a protection function, which prohibits writing of memory contents on a sector-specific or block-specific basis where the sector refers to a unit by which memory is erased at a time, and the block refers to a plurality of such units. Information about memory areas (sectors or blocks) that are protected from writing is stored in a nonvolatile memory as a protection status. A control circuit (state machine) of the nonvolatile semiconductor memory device refers to this information so as to prohibit the writing of protected areas.
A password mode is provided for the purpose of preventing the protection status from being changed through unauthorized access. In the password mode, the nonvolatile memory that holds the protection status is locked so as not to be rewritten, thereby making it sure that the protection status cannot be changed in the default operation. This lock is disengaged if a password entered from the exterior matches the password stored in the nonvolatile memory, thereby making it possible to change the protection status. This unlocking operation is called a password unlock.
The area of the nonvolatile memory where the password is stored is called an OTP (one time protect) area, which is allocated to outside the main memory space. Once protected, the OTP area can never be unlocked. No access can be made to the OTP area in the normal access mode, and an OTP mode needs to be engaged in order to access the OTP area. In the OTP mode, a selected sector of the main memory space is logically replaced by the OTP area, so that an address for accessing the selected sector can be used to access the OTP area. Since a password is stored in part of the OTP area, use of the OTP mode is necessary whenever the password function is used.
In the nonvolatile semiconductor memory device
10
of
FIG. 1
, it is assumed that such an OTP area
25
is provided in the bank-A
21
. When the OTP mode is activated, a selected sector of the bank-A
21
is logically replaced by the OTP area
25
, so that an address for accessing this selected sector can be used to access the OTP area
25
.
There is no need to inform users of the location where passwords are stored. In the password program operation (i.e., password setting operation), therefore, it is preferable to be able to set a password by entering only a password program command without entering an address that indicates a password address. Further, it is preferable to achieve a dual-operation in which a read operation on another bank can be performed simultaneously with the password program operation.
When a password program command is entered without an indication of any address, however, a bank selection status indicative of a bank other than the bank-A
21
may be latched by a bank selection circuit because an address input is of a “don't care” status. If the bank-C selection circuit
19
latches the bank selection status, for example, the bank-C
23
will be regarded as a bank to be written in response to the read/write-selection signal Y. In this case, it is not possible to carry out a read operation of the bank-C
23
. In this case, further, the bank-C
23
, rather than the bank-A
21
, is a bank to be written, so that it is
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Mai Son
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