Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2009-01-16
2010-12-28
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185050, C365S185120, C365S185020
Reexamination Certificate
active
07859898
ABSTRACT:
A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
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Arai Fumitaka
Sato Atsuhiro
Shuto Keiji
Graham Kretelia
Ho Hoai V
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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