Nonvolatile semiconductor memory device including correction...

Details Nonvolatile semiconductor memory device including correction... Nonvolatile semiconductor memory device including correction...

1999-06-29

2003-02-25

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185090

Reexamination Certificate

active

06525960

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and to a technique which is particularly effective when applied to a memory system for multivalued information in a nonvolatile semiconductor memory device. By way of example, the technique is effective when utilized for a nonvolatile memory device (hereinafter referred to simply as a flash memory) in which a plurality of pieces of stored information can be electrically erased all at once.
In a flash memory, nonvolatile memory elements each having a control gate and a floating gate are used as memory cells, and each memory cell can be constructed of a single transistor. In such a flash memory, when a write operation is executed, as illustrated in
FIG. 10
, the drain region of the nonvolatile memory element is set at, for example, about 5 V (volts), while a word line with the control gate CG connected thereto is set at, for example, about −11 V, whereby electric charges are extracted from the floating gate FG by means of a tunnel current so as to render the threshold voltage of the memory element low (logical value “0”). When an erase operation is executed, as illustrated in
FIG. 11
, a well region, the drain region and a source region are set at about −4 V, by way of example, while the control gate CG is set at a high voltage, such as 12 V, whereby negative charges are injected into the floating gate FG by the generation of a tunnel current so as to render the threshold voltage high (logical value “1”). Thus, data of 1 (one) bit is stored in one memory cell.
There has been proposed the concept of a so-called “multivalued” memory wherein data of 2 or more bits is stored in one memory cell for the purpose of enlarging the memory capacity. An invention concerning such a multivalued memory is disclosed in, for example, PCT/JP95/02260.
SUMMARY OF THE INVENTION
In the multivalued memory disclosed in PCT/JP95/02260, data is written in three stages, as shown in FIG.
12
. More specifically, from the starting point of an erase level (threshold voltage of about 5 V), a memory cell whose threshold voltage is nearest to the erase level is first subjected to a write operation, and memory cells whose threshold voltages are farther from the erase level are thereafter subjected to a write operation. This is intended to shorten the time period taken to write multivalued data. In a write operation in a flash memory, however, a high voltage is applied not only to the control gate of the selected memory cell, but also to the control gates of nonselected memory cells which are coupled with a word line common to that of the selected memory cell. As is known, accordingly, each of the nonselected memory cells is brought into a weak written (disturbed) state, so that the threshold voltage thereof may fluctuate to change stored data. This phenomenon is known as word line disturbance.
Besides, the inventors have found that the memory cell whose threshold voltage is nearer to the erase level is more susceptible to the fluctuation of the threshold voltage attributed to the word line disturbance, than the memory cell whose threshold voltage is farther. It is considered that this is because the initial threshold voltage of each memory cell at the time of manufacture of a memory chip is much lower than the erase level, and the memory cells have a tendency of reverting to their initial threshold voltage when subjected to a disturbance.
However, it has been found that the data writing system disclosed in PCT/JP95/02260 is subject to a problem in that the fluctuations of the threshold voltages attributed to word line disturbance are great because the write operation is performed from the memory cell of a threshold voltage nearest to the erase level, as compared to the memory cells having more distant threshold voltages. More specifically, the data writing method, as shown in
FIG. 12
, has a drawback in that the memory cell (of data “01”) having a threshold voltage (lower than 1.5 V) farthest from the erase level does not undergo word line disturbance even once, whereas the memory cell (of data “10”) having a threshold voltage (about 3.2 V) nearest to the erase level, being most susceptible to the word line disturbance, undergoes the disturbance twice on the average.
Further, it has been found that the data writing method disclosed in PCT/JP95/02260 has a drawback in that, since a write pulse is fed to all the memory cells whose threshold voltages are to be shifted in the write operation of the first stage, the peak current in the write operation increases and the average power consumption also increases.
An object of the present invention is to provide a multivalued memory type nonvolatile semiconductor memory device wherein the fluctuations in the threshold voltages of memory cells attributed to word line disturbance can be minimized.
Another object of the present invention is to provide a nonvolatile semiconductor memory device whose peak current and average power consumption in a write operation can be decreased.
The above and other objects and novel features of the present invention will become more apparent from the description of this specification taken in conjunction with the accompanying drawings.
A typical aspect of the present invention will be briefly outlined below.
In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are determined so as to store multivalued information in one memory cell, data is first written into a memory cell whose threshold voltage is the farthest from the erase level, and data is thereafter written into memory cells whose threshold voltages are nearer to the erase level, in succession. In other words, with the erase level used as a written state, data is first written into a memory cell having the lowest threshold voltage, and data is thereafter successively written into memory cells having higher threshold voltages.
Thus, the number of word line disturbances which affect the memory cell having a threshold voltage nearest to the erase level and being most influenced by word line disturbance can be decreased, and the fluctuation of the threshold voltages attributed to word line disturbance can be minimized.
Moreover, owing to this feature, the number of data lines which must be precharged by one writing operation and the total number of data lines which must be precharged from the start of a write operation to the end thereof can be made smaller than conventional, thereby to reduce the peak current and average power consumption in a write operation.


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