Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-02-12
2001-05-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06240021
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and, more specifically, to a nonvolatile semiconductor memory device using a stacked gate structure type transistor as a memory cell.
Conventionally a magnetic disk apparatus has been widely used as a nonvolatile memory device of an information processing apparatus. However, the magnetic disk apparatus has the following drawbacks. The apparatus is susceptible to a shock because it has a high-precision mechanical driving mechanism. Furthermore, the apparatus is not accessible to a storage memory at high speed because the access is done mechanically.
To overcome the above drawbacks, nonvolatile semiconductor memory devices having no mechanical driving mechanism have recently been developed as memory devices capable of high-speed access. A NOR type flash memory is known as one nonvolatile semiconductor memory device. The memory cell array of the flash memory is constituted of a plurality of stacked gate structure (floating gate electrode/control gate electrode) type transistors (memory cells) arranged in matrix.
When “0” information is written to the above flash memory, electrons are injected from a drain diffusion layer of a selected memory cell into a floating gate electrode thereof to increase a threshold voltage of the memory cell.
When “0” information is erased from the flash memory, a bias voltage is applied to the source diffusion layers of all memory cells to extract electrons from the floating gate electrodes, or a negative voltage is applied to the control gate electrodes, and electrons are extracted from the floating gate electrodes and applied to the entire surface of the channels to decrease a threshold voltage. This state is defined as “1” information.
In general, the erase speed varies from memory cell to memory cell. The electrons are therefore usually extracted until the threshold voltage of a memory cell whose erase speed is the lowest becomes not higher than a predetermined value. As a result, the threshold voltages of the memory cells after the erase operation have a distribution with a certain width.
When information is read out of the flash memory, the gate electrodes of non-selected memory cells are grounded to turn off the non-selected memory cells, and a voltage having a predetermined level is applied to the gate electrode of a selected memory cell.
Information (“1” or “0”) is determined according to whether a selected memory cell is turned on or off. When a memory cell is turned on, no information is written thereto and its threshold voltage is low. When a memory cell is turned off, information is written thereto and its threshold voltage is high.
In order to raise the read speed of memory cells, it is important to cause a large amount of current (on-current) to flow through memory cells to be turned on and reduce a leak current through memory cells to be turned off and a non-selected memory cell.
In order to increase the on-current, for example, it is necessary to make the threshold voltage of the memory cell as low as possible in the erase mode. If, however, the threshold voltage is too low, a leak current flows through a non-selected memory cells connected to a bit line selected in the read mode, even though its gate voltage corresponds to a ground potential.
As has been described above, the erase speed varies from memory cell to memory cell. For this reason, if an erase operation is performed until the memory cell whose erase speed is the lowest has a considerably low threshold voltage, the threshold voltage of a memory cell whose erase speed is high becomes 0V or lower (over-erasure). A large amount of leak current will therefore flow through a non-selected memory cell which is connected to a bit line selected in the read mode and whose erase speed is high.
FIG. 1
shows an example of distribution of threshold voltages of memory cells connected to one bit line after information is erased from these memory cells. In
FIG. 1
, Vthmax represents the threshold voltage of a memory cell the erase speed of which is the lowest, and Vthmin represents that of a memory cell the erase speed of which is the highest. Further, the solid line indicates a memory cell array of 1024 memory cells, and the broken line shows that of 64 memory cells.
1000 to 2000 memory cells are usually connected to one bit line. Recently a low-voltage operation and a low-power-consumption operation have strongly been required for nonvolatile semiconductor memory devices used in electronic equipment such as a portable information terminal.
To enable the low-voltage operation, a gate voltage VG has to lower as much as possible in the read mode. In this case, too, in order to obtain a considerable amount of read current &agr;, it is important to decrease the threshold voltage of a memory cell whose erase operation is completed and set a difference &bgr; between the gate voltage VG and threshold voltage Vthmax to be not less than a fixed value. In other words, the threshold voltage Vthmax has to be lowered in association with a decrease in gate voltage VG. If, however, the threshold voltage Vthmax is lowered, the threshold voltage Vthmin is lowered accordingly and an over-erasure is easy to occur, thereby causing the above-described problem that a large amount of leak current flows through non-selected memory cells connected to a bit line selected in the read mode.
As a method of resolving the above problem, it can be thought that a variation in erase speed among the memory cells is lessened and a difference between threshold voltages Vthmax and Vthmin is narrowed. However, the method is not the ultimate solution to the problem because the variation in erase speed cannot be avoided due to variations in precision of processing and current/voltage characteristics of an oxide film.
Furthermore, in order to secure a withstanding voltage between source and drain diffusion layers of a memory cell which decreases in accordance with miniaturization, a pocket region whose concentration is higher than that of a substrate has recently been formed by injecting impurities into around the drain diffusion layer, the conductivity type of the impurities being different from that of these diffusion layers. If, however, such a pocket region is formed, the following problem will arise. The parasitic junction capacitance of the drain diffusion layer increases and accordingly access time in the read mode is lengthened.
The following problem will also arise. If the gate length of a memory cell is decreased by miniaturization without forming a pocket region, the impurity concentration of the substrate need to increase and thus the increase in parasitic junction capacitance cannot be avoided.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the above problems and one object thereof is to provide a nonvolatile semiconductor memory device in which even though the threshold voltage of a memory cell is set low in an erase mode, an amount of leak current flowing through a memory cell connected to the same wiring as that of a control gate electrode of another memory cell from which information is to be read, can be reduced in the read mode.
Another object is to provide a nonvolatile semiconductor memory device capable of decreasing the parasitic junction capacitance of a drain diffusion layer and shortening access time (increasing access speed) even when a pocket region whose concentration is higher than that of a semiconductor substrate is formed or when the impurity concentration of the substrate is increased.
To attain the above objects, according to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a plurality of electrically erasable memory cells formed on the semiconductor substrate in matrix, and each including a source electrode and a drain electrode and having a stacked gate structure in which a control gate electrode and a floating gate electrode are formed one on another;
a fir
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Nelms David
Tran M.
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