Nonvolatile semiconductor memory device having reduced erase...

Details Nonvolatile semiconductor memory device having reduced erase... Nonvolatile semiconductor memory device having reduced erase...

2001-05-01

2003-02-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185270

Reexamination Certificate

active

06515908

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly a nonvolatile semiconductor memory device of a flash type.
2. Description of the Background Art
A nonvolatile semiconductor memory device of a flash type, i.e., a flash memory is functionally a nonvolatile semiconductor memory device of an entire memory block erasing type allowing electrical programming and erasing. Since such nonvolatile semiconductor memory devices are inexpensive and electrically erasable, they are in great demand for use in portable devices and others, and the research and development of them have been increasingly done in recent years. The flash memory uses transistors (which will be referred to as “memory transistors” hereinafter) as memory cells. These transistors include floating gates, and have variable threshold voltages, respectively.
The flash memory of the NOR type utilizes hot channel electrons for writing or programming, and therefore can achieve a high write speed.
The NOR type flash memory performs the erasing by changing the threshold voltage of memory transistor from a high to a low.
At present, a flash memory of a type, in which electrons in the floating gate are extracted through an edge into a source region in the erase operation, is the mainstream in the NOR type flash memories. In this invention, description will be made by way of example on applied voltages in the NOR type flash memory, in which electrons are extracted through a whole channel surface for performing the erasing. The NOR type flash memory, in which the erasing is performed by extracting electrons through the whole channel surface, allows scale-down of the cell sizes in contrast to the flash memory of the conventional edge extracting type.
FIG. 21
is a flowchart showing an example of the most simple erase sequence of the conventional flash memory.
Referring to
FIG. 21
, after an erase command is input in step S
101
, an erase pulse having a predetermined pulse strength is applied to a memory transistor in subsequent step S
102
.
Then, determination by an erase verify function is performed in step S
103
for determining whether erasing is completed or not.
When it is determined in step S
103
that information held in the memory cell is not erased, the processing returns to step S
102
, and steps S
102
and S
103
will be repeated until the threshold voltage of memory transistor decreases to or below an erase determination voltage so that the application of the erase pulse and the erase verify are repeated.
When it is determined in step S
103
that the threshold voltage of memory transistor is equal to or lower than the erase determination voltage, the processing advances to step S
104
, and the erasing operation ends.
FIG. 22
is a circuit diagram of a memory block for showing voltages, which are applied during application of the erase pulse in step S
102
shown in FIG.
21
.
Referring to
FIG. 22
, this memory block includes memory transistors; which are arranged in n rows and m columns, and each has a floating gate. For applying the erase pulse, a source line potential V
SL
and a well potential V
well
are both set to 8 V. All word lines for activating the memory transistors in the respective rows are set to −10 V. All bit lines BL
1
-BLm for reading data from the memory transistors in the respective columns are set to an open state.
FIG. 23
shows voltages applied to the memory transistor when the erase pulse is applied.
Referring to
FIG. 23
, source line potential V
SL
applied to a source of the memory transistor and well potential V
well
applied to a substrate of the memory transistor are both set to 8 V. A word line potential V
WL
applied to the word line for selecting the memory transistor is set to −10 V. In this state, a drain of the memory transistor is in the open state. Since a high electric field is applied not only between the gate and the source but also between the gate and the substrate, erasing is performed by extracting electrons through the whole channel surface of the memory transistor.
FIG. 24
is a circuit diagram showing voltages which are applied for erase verify performed in step S
103
of the sequence shown in FIG.
21
.
Referring to
FIG. 24
, well potential V
well
and source line potential V
SL
are both set to 0 V. Word line WLi which selects the memory transistor corresponding to the selected bit is set to 3.5 V, and the other word lines are all set to 0 V. Bit line BLj connected to the memory transistor corresponding to the selected bit is set to 1.0 V, and the other bit lines are all set to 0 V. The potentials are set as described above, and a current flowing through the memory transistor is determined, whereby it is determined whether erasing of memory transistor MT(i, j) is completed or not.
FIG. 25
shows voltages applied to the memory transistor corresponding to the selected bit in FIG.
24
.
Referring to
FIG. 25
, both the source and well of selected memory transistor MT(i, j) are set to 0 V. The memory transistor receives 3.5 V on its gate, and also receives 1.0 V on its drain.
Description will now be made on voltage setting in the read operation of the conventional flash memory.
FIG. 26
is a circuit diagram showing the voltage setting in the read operation of the conventional flash memory.
Referring to
FIG. 26
, word line WLi which is connected to the gate of the memory transistor corresponding to the selected bit is set to 4.5 V, and the other word lines are all set to 0 V. In this state, source line potential V
SL
and well potential V
well
are both set to 0 V.
FIG. 27
shows potentials applied to the memory transistor which is selected in the read operation shown in FIG.
26
.
Referring to
FIG. 27
, both the source and well of the memory transistor corresponding to the selected bit are set to 0 V. The drain carries 1.0 V, and the gate carries 4.5 V. In this state, when the threshold voltage of memory transistor is high, a current does not flow from the drain to the source. When the threshold voltage of memory transistor is low, a current flows from the drain to the source. By detecting this current, it can be determined whether data is already programmed into the memory transistor or not.
When an erase sequence of the conventional flash memory shown in
FIG. 21
is used, such a problem may arise that a part of the memory transistors are over-erased. The over-erased state will now be described.
FIG. 28
shows a distribution of the threshold voltages before application of the erase pulse.
Referring to
FIG. 28
, a programmed state where the memory transistor has stored “0” and an erased state where the memory transistor has stored “1” are present in the initial state of the erasing operation, i.e., before the erase command is applied in step S
101
in FIG.
21
. The ordinate in
FIG. 28
gives the number of memory transistors holding the respective threshold voltages in the memory block.
In the NOR type flash memory, the state where the threshold voltage is high corresponds to the programmed state, i.e., the state where “0” is held. The state where the threshold voltage is low corresponds to the erased state, i.e., the state where “1” is held.
In the state shown in
FIG. 28
, the memory block has already stored data through the preceding sequence, and the numbers of memory transistors in the programmed state and the erased state depend on this stored state, respectively. The memory transistors in the programmed state have the threshold voltages distributed in the range not lower than 5.5 V, and the memory transistors in the erased state have the threshold voltages distributed in a range not exceeding 3.5 V.
FIG. 29
shows an incompletely erased state where the data in all the bits are not completely erased even after the erase pulse was applied in the erase sequence shown in FIG.
21
.
Referring to
FIGS. 21 and 29
, the erase pulse of a predetermined width is applied collectively to all the memory transistors in the memory block in step S
102
. Thereby, erasing

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