Nonvolatile semiconductor memory device having reduced...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185050, C365S185180, C365S185230, C365S210130

Reexamination Certificate

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11329036

ABSTRACT:
A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.

REFERENCES:
patent: 4972378 (1990-11-01), Kitagawa et al.
patent: 5016216 (1991-05-01), Ali
patent: 5689468 (1997-11-01), Ihara
patent: 6829171 (2004-12-01), Ooishi
patent: 6885579 (2005-04-01), Sakimura et al.
patent: 2000-285692 (2000-10-01), None

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