Nonvolatile semiconductor memory device having multi-level...

Details Nonvolatile semiconductor memory device having multi-level... Nonvolatile semiconductor memory device having multi-level...

2008-05-13

2008-05-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S189050, C365S185170

Reexamination Certificate

active

11607027

ABSTRACT:
A non-volatile semiconductor memory device includes a memory array having nonvolatile memory cells. The memory device also includes a page buffer coupled to the memory array through first and second common bit lines and configured to map a set of first to third bit data to threshold voltage levels of a pair of first and second memory cells. The memory device also includes a row decoder configured to control a word line of a selected memory cell of the memory array. The page buffer includes a switch, a first latch block, a second latch block, a dumping block, and an output block.

REFERENCES:
patent: 6996014 (2006-02-01), Lee et al.
patent: 7187584 (2007-03-01), Chang
patent: 7190618 (2007-03-01), Byeon
patent: 1020000059746 (2000-10-01), None
patent: 1020050094569 (2005-09-01), None
patent: 1020050095191 (2005-09-01), None

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