Nonvolatile semiconductor memory device having floating gate ele

Details Nonvolatile semiconductor memory device having floating gate ele Nonvolatile semiconductor memory device having floating gate ele

1997-09-23

1999-05-04

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 257321, 257322, G11C 1604, H01L 29788

Patent

active

059010843

ABSTRACT:
A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.

REFERENCES:
patent: 3744036 (1973-07-01), Frohman-Bentchkowsky
patent: 5260593 (1993-11-01), Lee
patent: 5650649 (1997-07-01), Tsukiji
"Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness" by Naruke et al, IEDM Tech. Dig. 1988, pp. 424-427.
"Stress-Induced Current in Thin Silicon Dioxide Films" by Moazzami et al, IEDM Tech. Dig. 1992, pp. 139-142.
"Hole Infection SiO.sub.2 Breakdown Model for Very low Voltage Lifetime Extrapolation" by Schuegraf et al, IEEE Transactions on Electron Devices, vol. 41, No. 5, May 1994, pp. 761-767.
"A Quantitative Analysis of Stress Induced Excess Current (SIEC) in SiO.sub.2 Films" by Sakakibara et al, IEEE Intl. Reliability Physics Proceedings, Apr. 30, May 1,2, 1996, pp. 100-107.

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